LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 16

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Secondary Clock/Control Sources
LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the
rest from routing. Figure 2-11 shows the secondary clock sources.
Figure 2-11. Secondary Clock Sources
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
Routing
Routing
From
From
Routing
Routing
From
From
Secondary Clock Sources
Clock
Clock
Input
Input
2-13
Clock
Clock
Input
Input
Routing
Routing
From
From
LatticeECP2/M Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Architecture