LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 47

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further
information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional
technical information at the end of this data sheet.
Table 2-13. Supported Input Standards
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI 33
HSTL18 Class I, II
HSTL15 Class I
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I, II
Differential Interfaces
Differential SSTL18 Class I, II
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I
Differential HSTL18 Class I, II
LVDS, MLVDS, LVPECL, BLVDS, RSDS
1 When not specified, V
Input Standard
CCIO
can be set anywhere in the valid operating range (page 3-1).
V
2-44
REF
0.75
1.25
0.9
1.5
0.9
—
—
—
—
—
—
—
—
—
—
—
—
—
(Nom.)
LatticeECP2/M Family Data Sheet
V
CCIO
1.8
1.5
3.3
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Nom.)
Architecture