LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 14
LFE2M35E-6FN484C
Manufacturer Part Number
LFE2M35E-6FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-6FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
357 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
No. Of Logic Blocks
34000
No. Of Macrocells
16000
No. Of Speed Grades
6
Total Ram Bits
2101Kbit
No. Of I/o's
303
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 2-9. Clock Divider Connections
Clock Distribution Network
LatticeECP2/M devices have eight quadrant-based primary clocks and eight flexible region-based secondary
clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high
speed interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These
clock inputs are fed throughout the chip via a clock distribution system.
Primary Clock Sources
LatticeECP2/M devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs, CLK-
DIV outputs, dedicated clock inputs and routing. LatticeECP2/M devices have two to eight sysCLOCK PLLs and
two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side
of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock
inputs on the device. Figure 2-10 shows the primary clock sources.
CLKOP (GPLL)
CLKOS (GPLL)
CLKOP (DLL)
CLKOS (DLL)
PLL PAD
Routing
CLKO
RELEASE
RST
2-11
CLKDIV
LatticeECP2/M Family Data Sheet
÷1
÷2
÷4
÷8
Architecture
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