LIS302DLTR STMicroelectronics, LIS302DLTR Datasheet - Page 28

ACCELEROMETER 3AXIS MEMS 14-LGA

LIS302DLTR

Manufacturer Part Number
LIS302DLTR
Description
ACCELEROMETER 3AXIS MEMS 14-LGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of LIS302DLTR

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Axis
X, Y, Z
Acceleration Range
±2.3g, 9.2g
Sensitivity
18mg/digit, 72mg/digit
Voltage - Supply
2.16 V ~ 3.6 V
Output Type
Digital
Bandwidth
100Hz ~ 400Hz Selectable
Interface
I²C, SPI
Mounting Type
Surface Mount
Package / Case
14-LGA
Sensing Axis
X, Y, Z
Acceleration
2 g, 8 g
Digital Output - Number Of Bits
8 bit
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.16 V
Supply Current
0.3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Digital Output - Bus Interface
I2C, SPI
Shutdown
Yes
For Use With
497-9047 - BOARD DEMO ACCELEROMETER DIL24497-8373 - BOARD EVAL EXTENSION SN250497-8204 - BOARD ADAPTER LIS302SG DIL24497-8203 - BOARD DEMO LIS302SG497-6404 - BOARD EVAL SPZB260 MOD FOR STR9497-6342 - BOARD EVALUATION FOR LIS302DL497-6246 - BOARD EVAL ACCELEROM LIS302ALK497-6227 - BOARD ADAPTER 20DIP LIS3LV02DL497-6226 - BOARD EVAL ACCELEROM LIS3LV02DL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5911-2

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Register description
7.4
7.5
28/42
Table 22.
CTRL_REG3 [Interrupt CTRL register] (22h)
Table 23.
Table 24.
Table 25.
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g.
This allows to overcome the settling time of the high pass filter.
IHL
PP_OD
I2CFG2
I2CFG1
I2CFG0
I1CFG2
I1CFG1
I1CFG0
IHL
I1(2)_CFG2
HP_coeff2,1
00
01
10
11
0
0
0
0
1
1
High pass filter cut-off frequency configuration
CTRL_REG3 (22h) register
CTRL_REG3 (22h) register description
CTRL_REG3 (22h) truth table
PP_OD
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Data Signal on Int2 pad control bits. Default value 000.
(see table below)
Data Signal on Int1 pad control bits. Default value 000.
(see table below)
I1(2)_CFG1
I2CFG2
0
0
1
1
0
1
(DR=100 Hz)
ft (Hz)
I2CFG1
0.25
0.5
2
1
I1(2)_CFG0
I2CFG0
0
1
0
1
0
1
I1CFG2
FF_WU_1 or FF_WU_2
(DR=400 Hz)
Click interrupt
Int1(2) Pad
Data ready
FF_WU_1
FF_WU_2
I1CFG1
ft (Hz)
GND
8
4
2
1
LIS302DL
I1CFG0

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