ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 16

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Table 3. PLD Clock Frequency (kHz) PLD Prescaler Divider
Because the ispPAC-POWR1208P1’s PLD array is clocked from a divided-down version of the device’s 1MHz main
clock, special considerations must be observed for asserting input data if it is to be reliably recognized by state
machines implemented using the device. Data presented to the IN1 through IN4 digital inputs must be asserted for
a minimum of at least one PLD clock period (4µs – 512µs depending on the PLD prescaler setting) to be recog-
nized. For data presented to the VMON inputs, this minimum assertion time may need to be increased to account
for the behavior of the VMON samplers and digital filters (when enabled).
The Timer Clock Pre-Scaler divides the internal 1MHz oscillator (or external clock, if selected) down before it gen-
erates the clock for the four programmable timers. The pre-scaler has eight different divider ratios, shown in
Table 4. Each divider ratio provides a range of intervals to which each of the four timers may be independently pro-
grammed. Please note that since there is only one prescaler, all of the timer intervals must lie within the range
associated with the selected prescaler value.
Table 4. Timer Values
1. Timer values based on 1MHz clock.
0.032 ms
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
62.5 kHz
÷ ÷ ÷ ÷ 16
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
31.2 kHz
2.048ms
÷ ÷ ÷ ÷ 32
1
1. Frequency values based on 1MHz clock
PLD Prescaler Divider
16.384 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
15.6 kHz
2.048ms
÷ ÷ ÷ ÷ 64
128
256
512
16
32
64
4
8
16.384 ms
32.768 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
7.8 kHz
÷ ÷ ÷ ÷ 128
16
16.384 ms
32.768 ms
65.536 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
3.9 kHz
PLD Clock Frequency (kHz)
÷ ÷ ÷ ÷ 256
1
ispPAC-POWR1208P1 Data Sheet
62.5
31.3
15.6
250
125
7.8
3.9
2.0
131.072 ms
16.384 ms
32.768 ms
65.536 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
2.0 kHz
÷ ÷ ÷ ÷ 512
131.072 ms
262.144 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
2.048ms
1.0 kHz
÷ ÷ ÷ ÷ 1024
131.072 ms
262.144 ms
524.288 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
0.5 kHz
÷ ÷ ÷ ÷ 2048