ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 2

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Power Supply Sequence Controller and Monitor
The ispPAC-POWR1208P1 device is specifically designed as a fully-programmable power supply sequencing con-
troller and monitor for managing up to eight separate power supplies, as well as monitoring up to 12 analog inputs
or supplies. The ispPAC-POWR1208P1 device contains an internal PLD that is programmable by the user to imple-
ment digital logic functions and control state machines. The internal PLD connects to four programmable timers,
special purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked
by either an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as 12 independent comparators, each with 384 programmable trip-point set-
tings ranging from 0.68V to 5.392V in roughly 0.5% steps. An additional low-voltage threshold (80mV) is also pro-
vided for sensing power-off conditions.
The voltage monitors incorporate two features designed to increase their robustness. The first is a small amount of
hysteresis. In general, more hysteresis implies more noise immunity, but as trip-points decrease a fixed amount of
hysteresis would adversely affect the trip-point accuracy. For this reason the ispPAC-POWR1208P1’s voltage mon-
itors use a scheme in which hysteresis scales with trip-point voltages remaining at a nearly constant 0.5% of the
selected trip-point. Hysteresis is 30mV for a 5.932V trip-point and scales down to 4mV for a 0.68V trip-point.
The second feature that increases the voltage monitor’s robustness are a synchronizer and digital filter in each
monitor circuit. The filter may be optionally enabled to provide higher noise immunity at the cost of a somewhat
increased response time.
The programmable logic functions consist of a block of 36 inputs with 81 product terms and 16 macrocells. The
architecture supports the steering of product terms to enhance the overall usability.
Output pins are configurable in two different modes. There are eight outputs for controlling eight different power
supplies. OUT5-OUT8 are open-drain outputs for interfacing to other circuits. The HVOUT1-HVOUT4 pins can be
programmed individually as open-drain outputs or as high voltage FET gate drivers. As high voltage FET gate
driver outputs, they can be used to drive an external N-Channel MOSFET as a switch to control the voltage ramp-
up of the target board. The four HVOUT drivers have programmable current and voltage levels.
Figure 1. ispPAC-POWR1208P1 Block Diagram
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
RESET
IN1
IN2
IN3
IN4
Analog
Digital
Inputs
Inputs
5
12
36 I/P & 16
Controller
Sequence
4 Timers
Macrocell
Internal
250kHz
8
CPLD
GLB
OSC
CLKIO
2
ispPAC-POWR1208P1
4
4
High Voltage
ispPAC-POWR1208P1 Data Sheet
Comparator
Outputs
Outputs
Outputs
Logic
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
VDD
HVOUT1
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8