ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 28

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Figure 16. UES Register
PROGUES – This instruction will program the content of the UES Register into the UES E
device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs
into the SAFESTATE.
Notes:
In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in
which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E
using the corresponding erase instruction.
Application Example
The ispPAC-POWR1208P1 device has 12 comparators to monitor various power supply levels. The comparators
each have a programmable trip point that is programmed by the user at design time. The output of the comparators
are latched and optionally filtered before being fed into the PLD logic array to drive the state machine logic or mon-
itor logic. The comparator’s filtered outputs COMP1...COMP8 are also routed to external pins to be monitored
directly or can be used to drive additional control logic if expansion is required. The comparator outputs are open-
drain type output buffers and require a pull up resistor to drive a logic high. All 12 comparators have hysteresis, the
hysteresis is dependent on the voltage trip point scale that is set, it ranges from 4mV for a 0.680V trip point to
30mV for a 5.93V trip point. The comparators can be set with a trip point from 0.68V to 5.93V, with 384 different val-
ues. The application diagram shows a set-up that can monitor and control multiple power supplies. The ispPAC-
POWR1208P1 device controls FET switches to ramp the supplies at different slew rates and time delays. The digi-
tal outputs and inputs are also used to interface with the board that is being powered up.
To reduce the possibility of RF oscillation, a gate resistor (R
FET power switch. This resistor should be placed physically close to the MOSFET gate terminal, and connected by
as short a PCB trace as is feasible. An appropriate value for these gate resistors is highly dependent on both the
characteristics of the MOSFET being used and the circumstances of the application, but will often be in the range
of 10Ω to 100Ω.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
28
Bit
7
G
) is often inserted in series with the gate of the MOS-
Bit
6
Bit
5
ispPAC-POWR1208P1 Data Sheet
Bit
4
2
Bit
3
CMOS bits need to be erased
Bit
2
2
CMOS memory. The
Bit
1
Bit
0
TDO