ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 18

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Master-Slave and PLD Expansion Modes
To support designs requiring more I/O or logic resources than those provided by the ispPAC-POWR1208P1, it is
possible to gang a number of devices together, or to add a CPLD to provide additional logic. Figure 7 shows an
example of slaving a CPLD and two ispPAC-POWR1208P1’s to a single master device
Figure 7. Example of ispPAC-POWR1208P1’s and CPLD in Expansion Mode
In this circuit a 1 MHz CLK output is broadcast from the master device to all of the slave devices. The PLD pres-
caler should be set identically for both the master and slave ispPAC device to ensure synchronous operation. In the
case of the CPLD, some internal logic will need to be used to essentially replicate the function of the ispPAC
devices’ PLD prescaler to ensure that it also operates synchronously.
The POR (power-on reset) signal from the master device is broadcast to all of the slave devices, holding them in a
reset state until the master device’s power-on-reset sequence completes. Because each of the ispPAC slave
devices have their own power-on-reset circuitry, their signals are wire-OR’ed together and fed back into the master
device’s RESET. This causes all of the devices to remain in a reset state until all power-on-reset sequences have
been successfully completed.
While it is possible to also slave ispPAC-POWR1208 and ispPAC-POWR604 devices to an ispPAC-POWR1208P1,
the converse is not true. This is because the ispPAC-POWR1208 and 604 devices operate from a 250kHz internal
clock, while the ispPAC-POWR1208P1 requires a 1MHz clock to maintain proper internal operation. Table 5 sum-
marizes the requirements for slaving a device to the ispPAC-POWR1208P1.
Connection
Wired
‘OR’
V+
R
RESET
PU
POR
POR
POWR1208P1
POWR1208P1
POWR1208P1
ispPAC-
ispPAC-
ispPAC-
Master
Slave
Slave
CLK
CLK
CLK
POR
RESET
RESET
18
V+
R
PU
ispPAC-POWR1208P1 Data Sheet
CLOCK
RESET
Expansion
Divider
Clock
PLD