ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 22

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
ispPAC-POWR1208P1 Data Sheet
IEEE Standard 1149.1 Interface
Communication with the ispPAC-POWR1208P1 is facilitated via an IEEE 1149.1 test access port (TAP). It is used
by the ispPAC-POWR1208P1 as a serial programming interface, and not for boundary scan test purposes. There
are no boundary scan logic registers in the ispPAC-POWR1208P1 architecture. This does not prevent the ispPAC-
POWR1208P1 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 com-
pliant devices. Since the ispPAC-POWR1208P1 is used to powerup other devices, it should be programmed in a
separate chain from PLDs, FPGAs or other JTAG devices.
A brief description of the ispPAC-POWR1208P1 serial interface follows. For complete details of the reference spec-
ification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-
1990 (which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1208P1. The TAP controller is a state machine driven with mode and clock inputs. Under the correct
protocol, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing various registers, shifting data in,
and then executing the respective program instruction. The programming instructions transfer the data into internal
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CMOS memory. It is these non-volatile memory cells that determine the configuration of the ispPAC-
POWR1208P1. By cycling the TAP controller through the necessary states, data can also be shifted out of the var-
ious registers to verify the current ispPAC-POWR1208P1 configuration. Instructions exist to access all data regis-
ters and perform internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional
user data registers that are defined by the manufacturer. The two required registers are the bypass and boundary-
scan registers. For ispPAC-POWR1208P1, the bypass register is a 1-bit shift register that provides a short path
through the device when boundary testing or other operations are not being performed. The ispPAC-
POWR1208P1, as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All
instructions relating to boundary scan operations place the ispPAC-POWR1208P1 in the BYPASS mode to main-
tain compliance with the specification.
The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPAC-
POWR1208P1. Six additional user data registers are included in the TAP of the ispPAC-POWR1208P1 as shown in
Figure 11. Most of these additional registers are used to program and verify the analog configuration (CFG) and
PLD bits. A status register is also provided to read the status of the twelve analog comparators.
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