ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 19

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Table 5. ispPAC-POWR1208P1 Expansion Requirements
Note that because different slave devices impose different requirements for master clock output frequency, there
are limitations on what types of slave devices may be operated synchronously from a single master. For example, it
is not generally possible to slave both ispPAC-POWR1208P1’s and ispPAC-POWR1208’s (or POWR604’s) together
to a single ispPAC-POWR1208P1.
Output Configuration Modes
The output pins for the ispPAC-POWR1208P1 device are programmable for different functional modes. The four
outputs HVOUT1-HVOUT4, can be used as FET gate drivers or be programmed as open-drain digital outputs.
Figure 8 explains the details of the gate driver mode.
Figure 8. Basic Function Diagram for an Output in High-Voltage MOSFET Gate Driver Mode
Figure 8 shows an output programmed for gate driver mode. In this mode the output is a current source that is pro-
grammable between 0.5µA to 50µA. The maximum voltage that the output level at the pin will rise is also program-
mable. The levels required depend on the gate-to-source threshold of the FET and the supply voltage. The
maximum level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load volt-
age at the FET’s source, since the source pin of the FET is tied to the supply of the target board. When the HVOUT
pin is sourcing current, charging a FET gate, the current is programmable between 0.5µA and 50µA. When the
driver is turned to the off state, the driver will sink current to ground through the 8kΩ resistor.
ispPAC-POWR1208P1
ispPAC-POWR1208
ispPAC-POWR604
CPLD or FPGA
Slave Device
From Sequence
(8-12V)
Controller
V
Digital In
PP
External Clock Mode
External Clock Mode
Clock Prescaler implemented in logic
No Clock Prescaler
≈ 8kΩ
Slave Configuration
(0.5-50uA)
19
I
Source
ispPAC-POWR1208P1 Data Sheet
Select 1MHz Clock Output
Select PLD Prescaler Output
Select 1MHz Clock Output
Select PLD Prescaler output
Output to
IC Pin
Master Configuration