ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 25

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Table 7. ispPAC-POWR1208P1 TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1208P1. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1208P1 has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 7.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR1208P1 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1208P1 and leaves it in
its functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
EXTEST
ADDPLD
DATAPLD
ERASEAND
ERASEARCH
PROGPLD
PROGESF
BYPASS
READPLD
DISCHARGE
ADDCFG
DATACFG
ERASECFG
PROGCFG
READCFG
CFGBE
SAFESTATE
PROGRAMEN
IDCODE
PROGRAMDIS
ADDSTATUS
SAMPLE
ERASEUES
SHIFTUES
PROGUES
BYPASS
1. When these instructions are executed, the outputs are placed in the same mode as the instruction SAFESTATE (as
2. Instructions that erase or program the E
described later) to prevent invalid and potentially destructive power supply sequencing.
maintained at 3.0V to 5.5V.
Instruction
1, 2
1
1
1
1
1
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
1, 2
1
1
1, 2
1
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
1xxxxx
Code
2
CMOS memory must be executed only when the supply to the device is
External Test. Defaults to BYPASS.
Address PLD address register (75 bits).
Address PLD column data register (81 bits).
Bulk Erase AND array.
Bulk Erase Architect array.
Program PLD column data register into E
Program the Electronic Security Fuse bit.
Bypass (connect TDI to TDO).
Reads PLD column data from E
Fast VPP discharge.
Address CFG array address (4 bits).
Address CFG data (41 bits).
Bulk Erase CFG data.
Program CFG data register into E
Read CFG column data from E
Bulk Erase all E
Digital outputs hiZ (FET pulled L)
Enable program mode (SAFESTATE IO)
Address Identification Code data register (32 bits).
Disable Program mode (normal IO)
Address STATUS register (12 bits).
Sample/Preload. Default to Bypass.
Bulk Erase UES.
Reads UES data from E
Program UES data register into E
Bypass (connect TDI to TDO).
25
2
memory (CFG, PLD, USE, and ESF).
2
and selects the UES register (16 bits).
Description
ispPAC-POWR1208P1 Data Sheet
2
2
to the register (41 bits).
to the register (81 bits).
2
2
.
.
2
.