ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 26

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
device type and version code (Figure 13). Access to the Identification Register is immediately available, via a TAP
data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 7.
Figure 13. ID Code
ispPAC-POWR1208P1 Specific Instructions
There are 21 unique instructions specified by Lattice for the ispPAC-POWR1208P1. These instructions are prima-
rily used to interface to the various user registers and the E
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 7.
ADDPLD – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or
read operations. This instruction also forces the outputs into the SAFESTATE.
DATAPLD – This instruction is used to shift PLD data into the register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASEAND – This instruction will bulk erase the PLD AND array. The action occurs at the second rising edge of
TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
ERASEARCH – This instruction will bulk erase the PLD ARCH array. The action occurs at the second rising edge
of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
PROGPLD – This instruction programs the selected PLD AND/ARCH array column. The specific column is prese-
lected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction
also forces the outputs into the SAFESTATE.
PROGESF – This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit
protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
READPLD – This instruction is used to read the content of the selected PLD AND/ARCH array column. This spe-
cific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAF-
ESTATE.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR1208P1 for a read cycle. This instruction also forces the outputs into
the SAFESTATE.
E
MSB
XXXX / 0000 0001 0100 0010 / 0000 0100 001 / 1
2
Configured
Version
(4 bits)
0142h = ispPAC-POWR1208P1
Part Number
(16 bits)
26
2
Lattice Semiconductor
CMOS non-volatile memory. Additional instructions are
JEDEC Manufacturer
Identity Code for
(11 bits)
ispPAC-POWR1208P1 Data Sheet
per 1149.1-1990
Constant 1
LSB
(1 bit)