ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 4

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond these listed values may cause perma-
nent damage to the device. Functional operation of the device at these or any other conditions outside those indi-
cated in the operating sections of this specification is not implied.
Pin Descriptions (Continued)
1. RESET is an active low INPUT pin, external pull-up resistor to V
2. V
3. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time.
4. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional exter-
V
V
HVOUTmax HVOUT pin voltage, max = V
V
VMON
V
T
T
T
1. V
2. Digital inputs are tolerant up to 5.5V, independent of the V
A
S
SOL
DD
DDINP
IN
TRI
Number
Symbol
and may turn “ON” or “OFF” the output pins, including the HVOUT pins depending on the polarity configuration of the outputs in the PLD. If
a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals. The
RESET should be used if multiple ispPAC-POWR1208P1 devices are cascaded together in expansion mode.
In output mode it is an open-drain type pin and requires an external pull-up resistor. Multiple ispPAC-POWR1208P1 devices can be tied
together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. The slave needs
to be set up using the clock as an input.
nal circuitry should be connected to this pin.
supply voltage for the given input logic range.
2
DDINP
DDINP
39
40
41
42
43
44
1
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
can be chosen independent of V
CREF
VMON8
VMON9
VMON10
VMON11
VMON12
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V
Tristated or open drain output, external voltage applied (CLK
pin 26 pull-up ≤ V
Storage temperature
Ambient temperature with power applied
Maximum soldering temperature (10 sec. at 1/16 in.)
Name
Reference
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
DD
).
Pin Type
MON
4
DD.
Parameter
It is used to set the logic threshold only to the four logic inputs IN1-IN4.
voltage monitor inputs
DD
+ 9V
DDINP
Reference for Internal Use, Decoupling Capacitor (.1uf Required,
CREF to GND)
Voltage Monitor Input 8
Voltage Monitor Input 9
Voltage Monitor Input 10
Voltage Monitor Input 11
Voltage Monitor Input 12
DD
voltage.
4
is required. When driven low it resets all internal PLD flip-flops to zero,
ispPAC-POWR1208P1 Data Sheet
Conditions
—
—
—
—
—
—
—
—
—
Description
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-65
-55
—
DDINP
Max.
pin with appropriate
150
125
260
6.0
6.0
6.0
7.0
6.0
15
Units
°C
°C
°C
V
V
V
V
V
V