ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 32

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
Figure 20. PAC-Designer Functional Simulation Screen
In-System Programming
The ispPAC-POWR1208P1 is an in-system programmable device. This is accomplished by integrating all E
configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compli-
ant serial JTAG interface. Once a device is programmed, all configuration information is stored on-chip, in non-vol-
atile E
instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the
device, stored in E
user to store unique data such as ID codes, revision numbers or inventory control codes.
Electronic Security
An Electronic Security Fuse (ESF) bit is provided to prevent unauthorized readout of the E
programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased
by reprogramming the device; this way the original configuration cannot be examined or copied once programmed.
Usage of this feature is optional.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
The ispPAC-POWR1208P1 Design Kit includes an engineering prototype board that can be connected to the paral-
lel port of a PC using a Lattice ispDOWNLOAD cable. It demonstrates proper layout techniques for the ispPAC-
POWR1208P1 and can be used in real time to check circuit operation as part of the design process. LEDs are sup-
plied to debug designs without involving test equipment. Input and output connections as well as a “breadboard”
circuit area are provided to speed debugging of the circuit. The board includes an area for prototyping other circuits
and interconnect areas with pads for pins or cables. The user can check out designs on the hardware and make
necessary changes to the design for the function required.
2
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR1208P1
PAC-SYSPOWR1208P1
PACPOWR1208P1-EV
Part Number
2
CMOS memory. The ispPAC-POWR1208P1 contains 16 UES bits that can be configured by the
Complete system kit, evaluation board, ispDOWNLOAD Cable and software
Evaluation board only, with components, fully assembled
32
Description
ispPAC-POWR1208P1 Data Sheet
2
CMOS bit pattern. Once
2
CMOS