ISPPAC-POWR1208-01TN44I LATTICE SEMICONDUCTOR, ISPPAC-POWR1208-01TN44I Datasheet - Page 30

• Manufacturer Part Number: ISPPAC-POWR1208-01TN44I
• Description: ISP CONTROLLER, 1208, TQFP44, 5V
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPPAC-POWR1208-01TN44I

• Input Voltage: 2.7V To 5.5V
• Digital Ic Case Style: TQFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Operating Temperature Max: 85°C
• Operating Temperature: RoHS Compliant

Lattice Semiconductor
ispPAC-POWR1208P1 Data Sheet
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR1208P1 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 18) that allows the user to
set up the ispPAC-POWR1208P1 to perform given functions, such as timed sequences for power supply and mon-
itor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR1208P1. An extension to the schematic screen is the LogiBuilder
design environment (Figure 19) that is used to enter and edit control sequences. Again, user-friendly dialog boxes
are provided in this window to help the designer to quickly implement sequences that take advantage of the power-
ful built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the
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device is ready to program. A standard JTAG interface is used to program the E
CMOS memory. PAC-Designer
software supports downloading the device through the PC’s parallel port. The ispPAC-POWR1208P1 can be repro-
®
grammed using the software and ispDOWNLOAD
Cable assembly, to adjust for variations in supply timing,
sequencing or scaling of voltage monitor inputs.
Figure 18. PAC-Designer Schematic Screen
The user interface (Figure 18) provides access to various internal function blocks within the ispPAC-POWR1208P1
device.
Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
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