KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 11

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
Pin Description and I/O Assignment
November 2009
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Pin Name
RXM1
RXP1
TXM1
TXP1
VDDA_3.3
ISET
VDDA_1.8
RXM2
RXP2
AGND
TXM2
TXP2
NC
X1
X2
SMTXEN3
SMTXD33/
EN_REFCLKO_3
SMTXD32
SMTXD31
SMTXD30
GND
VDDIO
SMTXC3/
REFCLKI_3
SMTXER3/
MII_LINK_3
SMRXDV3
Type
lpu/O
Gnd
lpu/I
Gnd
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
P
P
P
I
I
I
I
I
I
(1)
Description
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
3.3V analog V
Set physical transmit output current.
Pull-down this pin with a 11.8K 1% resistor to ground.
1.8 analog VDD input power supply from VDDCO (pin 42) through external
Ferrite bead and capacitor.
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Analog ground.
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
Connect to Analog ground.
25 or 50MHz crystal/oscillator clock connections.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a
3.3V tolerant oscillator and X2 is a NC.
Note: Clock is +/- 50ppm for both crystal and oscillator.
Switch MII transmit enable
MLL/FLL: Switch MII transmit data bit 3
RLL: Strap option: RMII mode Clock selection
PU = Enable REFCLKO_3 output
PD = Disable REFCLKO_3 output
Switch MII transmit data bit 2
Switch MII transmit data bit 1
Switch MII transmit data bit 0
Digital ground
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well
decoupling capacitors.
MLL/FLL: Switch MII transmit clock (MII and SNI modes only)
RLL: Reference clock input
Note: pull up or down is needed if internal reference clock is used in RLL.
Switch MII transmit error in MII MAC mode
MII link indicator from host in MII PHY mode. High = No link.
Switch MII receive data valid
Strap option: Force duplex mode (P1DPX)
PU = port 1 default to full duplex mode if P1ANEN = 1 and auto-
negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0.
PD = port 1 default to half duplex mode if P1ANEN = 1 and auto-
negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0.
11
DD
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode.
KSZ8863MLL/FLL/RLL
M9999-110309-1.1