KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 28

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during
transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.
For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8863MLL/FLL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC
mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates
a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8863MLL/FLL. So, for PHY mode operation, if the device interfacing with the KSZ8863MLL/FLL has an MRXER input
pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8863MLL/FLL has an
MTXER input pin, it also needs to be tied low.
The KSZ8863MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link
status. If the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will
be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out.
Turbo MII Interface Operation
The switch MII interface also supports the turbo MII mode with 200Mbps rate (200Base-TX) by setting the register 2
bit[6]=1. When use the Turbo MII mode, the other side of the MII should also support 200Mbps rate. The Turbo MII can be
configured to PHY mode or MAC mode by the configuration pins. In PHY mode, the pins SMTXC and SMRXC will be 50
MHz clock output. In MAC mode, the pins SMTXC and SMRXC should be 50 MHz clock input.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
When EN_REFCLKO_3 is high, KSZ8863RLL will output a 50MHz in REFCLKO_3. Register 198 bit[3] is used to select
internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL will be
provided by the KSZ8863RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the
clock will provide to KSZ8863RLL via REFCLKI_3.
Note: If the reference clock is not provided by the KSZ8863RLL, this 50MHz reference clock has to be used in X1 pin instead of the 25MHz crystal since
the clock skew of these two clock sources will impact on the RMII timing. The SPIQ clock selection strapping option pin is connected to low to select the
50MHz input.
The RMII provided by the KSZ8863RLL is connected to the device’s third MAC. It complies with the RMII Specification.
The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal
description.
November 2009
1. ports 10Mbps and 100Mbps data rates.
2. Uses a single 50 MHz clock reference (provided internally or externally).
3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.
4. Contains two distinct groups of signals: one for transmission and the other for reception
Reg198[3]
0
0
1
1
EN_REFCLKO_3
0
1
1
0
Table 5. RMII Clock Setting
Clock Source
External 50MHz OSC
input to REFCLKI_3
REFCLKO_3 Output
Is Feedback to
REFCLKI_3
Internal Clock Source
REFCLKI_3 is
unconnected
28
Note
EN_REFCLKO_3 = 0
to Disable
REFCLKO_3 for better
EMI
EN_REFCLKO_3 = 1
to Enable
REFCLKO_3
EN_REFCLKO_3 = 1
to Enable
REFCLKO_3
Not suggest
KSZ8863MLL/FLL/RLL
M9999-110309-1.1