KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 56

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
September 2009
2-0
Bit
Bit
7
6
5
4
3
7
6
5
4
Sniffer Port
Receive
Sniff
Transmit
Sniff
Double Tag
User Priority
Ceiling
Port VLAN
membership
Enable 2
Queue Split
of Tx Queue
Ingress
VLAN
Filtering
Discard non
PVID
Packets
Force Flow
Control
Name
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
= 1, Port is designated as sniffer port and will transmit packets that are
monitored.
= 0, Port is a normal port
= 1, All packets received on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port”
= 0, no receive monitoring
= 1, All packets transmitted on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port”
= 0, no transmit monitoring
= 1, All packets will be tagged with port default tag of ingress port
regardless of the original packets are tagged or not
= 0, do not double tagged on all packets
= 1, if the packet’s “user priority field” is greater than the “user priority
field” in the port default tag register, replace the packet’s “user priority
field” with the “user priority field” in the port default tag register.
= 0, do not compare and replace the packet’s ‘user priority field”
Define the port’s egress port VLAN membership. The port can only
communicate within the membership. Bit 2 stands for port 3, bit 1 stands
for port 2, bit 0 stands for port 1.
An ‘1’ includes a port in the membership.
An ‘0’ excludes a port from membership.
Description
=1, Enable
It cannot be enable at the same time with split 4 queue at register 16,32
and 48 bit 0.
=0, Disable
= 1, the switch will discard packets whose VID port membership in
VLAN table bits [18:16] does not include the ingress port.
= 0, no ingress VLAN filtering.
= 1, the switch will discard packets whose VID does not match ingress
port default VID.
= 0, no packets will be discarded
= 1, will always enable full duplex flow control on the port, regardless of
AN result.
= 0, full duplex flow control is enabled based on AN result.
56
KSZ8863MLL/FLL/RLL
For port 1, SPIQ
Pin value during
For port 3, this
meaning. Flow
Default
SMRXD30 pin
pin (defult is
111
For port 2,
bit has no
0
0
0
0
0
Default
M9999-091009-1.1
reset:
PD)
0
0
0