KSZ8863RLL-EVAL Micrel Inc, KSZ8863RLL-EVAL Datasheet - Page 38

• Manufacturer Part Number: KSZ8863RLL-EVAL
• Description: BOARD EVALUATION FOR KSZ8863RLL
• Manufacturer: Micrel Inc

Specifications of KSZ8863RLL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3868

Micrel, Inc.
I2C Slave Serial Bus Configuration
In managed mode, the KSZ8863MLL/FLL/RLL can be configured as an I
device (external controller/CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly
accessed via registers 121 to 131.
In I
KSZ8863MLL/FLL/RLL’s 8-bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of
I
Two fixed 8-bit device addresses are used to address the KSZ8863MLL/FLL/RLL in I
other is for write. The addresses are as follow:
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the I
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down”
can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8863MLL/FLL/RLL can be configured as a SPI slave device. In this mode, a SPI master
device (external controller/CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly
accessed via registers 121 to 131.
The KSZ8863MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data
write. SPI multiple read and multiple write are also supported by the KSZ8863MLL/FLL/RLL to expedite register read back
and register configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8863MLL/FLL/RLL internal address counter increments
automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto
the KSZ8863MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-
asserting the SPISN signal to the KSZ8863MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN input
pin low after a byte (a register) is written. The KSZ8863MLL/FLL/RLL internal address counter increments automatically to
the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8863MLL/FLL/RLL
SDA input pin is written to the next register address. SPI multiple write continues until the SPI master device terminates it
by de-asserting the SPISN signal to the KSZ8863MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8863MLL/FLL/RLL internal address counter wraps back to register
address zero once the highest register address is reached. This feature allows all 198 KSZ8863MLL/FLL/RLL registers to
be read, or written with a single SPI command from any initial register address.
November 2009
2
C read/write operations and related timing information can be found in the AT24C02 Datasheet.
1. Enable I
2. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL. Configure the desired register settings in the
3. Read back and verify the register settings in the KSZ8863MLL/FLL/RLL, using the I
2
C
1011_1111 <read>
1011_1110 <write>
KSZ8863MLL/FLL/RLL, using the I
slave
2
C slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins PS[1:0] to “01”.
mode, the
KSZ8863MLL/FLL/RLL operates
2
C write operation.
38
like other
2
C slave device. In this mode, an I
I
2
C slave
2
C slave mode. One is for read; the
2
2
C read operation.
C slave serial bus:
devices.
KSZ8863MLL/FLL/RLL
M9999-110309-1.1
Addressing
2
C master
the