EP3C16F256I7 Altera, EP3C16F256I7 Datasheet
EP3C16F256I7
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EP3C16F256I7 Summary of contents
Page 1
... Cyclone III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com CIII5V1-1.0 Preliminary ...
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... Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to ...
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... Chapter 8. High-Speed Differential Interfaces in Cyclone III Devices Revised: March 2007 Part number: CIII51008-1.0 Chapter 9. External Memory Interfaces in Cyclone III Devices Revised: March 2007 Part number: CIII51009-1.0 Chapter 10. Configuring Cyclone III Devices Revised: March 2007 Part number: CIII51010.1.0 Altera Corporation - Preliminary Chapter Revision Dates iii ...
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... March 2007 Part number: CIII51013-1.0 Chapter 14. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices Revised: March 2007 Part number: CIII51014-1.0 Chapter 15. Package Information for Cyclone III Devices Revised: March 2007 Part number: CIII51015-1.0 iv Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... Chapter Revision Dates .......................................................................... iii About this Handbook ............................................................................. xiii How to Contact Altera .......................................................................................................................... xiii Typographic Conventions .................................................................................................................... xiii Section I. Device Core Chapter 1. Cyclone III Device Family Overview Cyclone III: Lowest System-Cost FPGAs ........................................................................................... 1–1 Features ................................................................................................................................................... 1–1 Reduced Cost .................................................................................................................................... 1–1 Lowest-Power 65-nm FPGA ........................................................................................................... 1–1 Increased System Integration ......................................................................................................... 1–1 Cyclone III Device Architecture .......................................................................................................... 1– ...
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... Clocking Modes ................................................................................................................................... 4–17 Independent Clock Mode .............................................................................................................. 4–18 Input/Output Clock Mode ........................................................................................................... 4–20 Read/Write Clock Mode ............................................................................................................... 4–23 Single-Clock Mode ......................................................................................................................... 4–25 Design Considerations ........................................................................................................................ 4–28 Read-During-Write Operations .................................................................................................... 4–28 Conflict Resolution ......................................................................................................................... 4–31 Power-Up Conditions and Memory Initialization .................................................................... 4–32 Power Management ....................................................................................................................... 4–32 vi Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... Post-scale Counter Cascading ...................................................................................................... 6–25 Programmable Duty Cycle ........................................................................................................... 6–26 PLL Control Signals ....................................................................................................................... 6–26 Clock Switchover ............................................................................................................................ 6–27 Manual Override ............................................................................................................................ 6–30 Phase-Shift Implementation ............................................................................................................... 6–33 PLL Cascading ..................................................................................................................................... 6–35 PLL Reconfiguration ........................................................................................................................... 6–37 PLL Reconfiguration Hardware Implementation ..................................................................... 6–37 Spread-Spectrum Clocking ................................................................................................................ 6–47 PLL Specifications ................................................................................................................................ 6–47 Altera Corporation vii ...
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... Differential Pad Placement Guidelines ....................................................................................... 7–32 V Pad Placement Guidelines ................................................................................................... 7–34 REF DC Guidelines ................................................................................................................................. 7–37 Conclusion ............................................................................................................................................ 7–38 Document Revision History ............................................................................................................... 7–38 Chapter 8. High-Speed Differential Interfaces in Cyclone III Devices Introduction ............................................................................................................................................ 8–1 Cyclone III High-Speed I/O Banks ................................................................................................................................................ 8–2 Cyclone III High-Speed viii Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... On-Chip Termination (OCT) ........................................................................................................ 9–18 PLL ................................................................................................................................................... 9–18 Conclusion ............................................................................................................................................ 9–19 Document Revision History ............................................................................................................... 9–19 Section III. Configuration, Hot Socketing, Remote Upgrades, and SEU Mitigation Chapter 10. Configuring Cyclone III Devices Introduction .......................................................................................................................................... 10–1 Configuration Devices ................................................................................................................... 10–2 Configuration Schemes ................................................................................................................. 10–2 Configuration File Format ............................................................................................................ 10–7 Altera Corporation ix ...
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... Cyclone III Hot-Socketing Specifications ......................................................................................... 11–1 Devices Can Be Driven Before Power-Up .................................................................................. 11–2 I/O Pins Remain Tri-Stated During Power-Up ......................................................................... 11–2 Hot-Socketing Feature Implementation in Cyclone III Devices ................................................... 11–3 Power-On Reset Circuitry .................................................................................................................. 11–5 Wake-Up Time for Cyclone III Devices ...................................................................................... 11–5 Conclusion ........................................................................................................................................... 11–7 x Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... IEEE Std. 1149.1 BST Architecture .................................................................................................... 14–2 IEEE Std. 1149.1 Boundary-Scan Register ........................................................................................ 14–4 Boundary-Scan Cells of a Cyclone III Device I/O Pin .............................................................. 14–5 IEEE Std. 1149.1 BST Operation Control .......................................................................................... 14–7 SAMPLE/PRELOAD Instruction Mode ................................................................................... 14–13 EXTEST Instruction Mode .......................................................................................................... 14–14 BYPASS Instruction Mode .......................................................................................................... 14–16 Altera Corporation xi ...
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... Boundary-Scan Description Language (BSDL) Support .............................................................. 14–23 Conclusion .......................................................................................................................................... 14–23 References ........................................................................................................................................... 14–23 Document Revision History ............................................................................................................. 14–23 Section IV. Packaging Information Chapter 15. Package Information for Cyclone III Devices Introduction .......................................................................................................................................... 15–1 Thermal Resistance .............................................................................................................................. 15–2 Package Outlines ................................................................................................................................. 15–2 Document Revision History ............................................................................................................... 15–2 xii Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... This handbook provides comprehensive information about the Altera Cyclone How to Contact For the most up-to-date information about Altera products the Altera world-wide web site at www.altera.com. For technical support on Altera this product www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. ...
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... The feet direct you to more information on a particular topic. xiv Preliminary Meaning , PIA input. , Active-low signals are denoted by suffix c:\qdesigns\tutorial\chiptrip.gdf SUBDESIGN ), as well as logic function names (e.g., Cyclone III Device Handbook, Volume 1 data1 n resetn , e.g Also, sections of an TRI ) are shown in Altera Corporation - Preliminary , ...
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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Altera Corporation- Preliminary Section I. Device Core ® III device family, which is the most architecturally advanced, ...
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... Device Core Section I–2 Cyclone III Device Handbook, Volume 1 Altera Corporation ...
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... Lowest low-power (LP) process technology with additional silicon optimizations System-Cost and software features to minimize power consumption. With this third generation in the Cyclone series, Altera broadens the number of high FPGAs volume, cost-sensitive applications that can benefit from FPGAs. Features Cyclone III devices are designed to offer low-power consumption and increased system integration at reduced cost ...
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... Multi-value on-chip termination (OCT) support with calibration feature to eliminate variations over PVT Adjustable I/O slew rates to improve signal integrity Support for low-cost Altera serial flash and commodity parallel flash configuration devices from Intel and Spansion Remote system upgrade feature without requiring an external ...
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... This allows designers to optimize density and cost as the design evolves. Table 1–2 counts. The highest I/O count in the family is delivered by the EP3C40. Altera Corporation-Preliminary March 2007 displays Cyclone III device family features. EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 ...
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... Note to Table 1–2: (1) For more information on Device Packaging Specifications, refer to the support section of the Altera website. (http://www.altera.com/support/devices/packaging/specifications/pkg-pin/spe-index.html). (2) The numbers are the maximum I/O counts (including clock input pins) supported by the device-package combination and can be affected by the configuration scheme selected for the device. ...
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... Device embedded multiplier, I/O, and packaging options. Cyclone III FPGAs support numerous external memory interfaces and I/O protocols Architecture common in high volume applications. Figure 1–1 Altera Corporation-Preliminary March 2007 256-pin 256-pin 324-pin FBGA UBGA ...
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... For more information, refer to the Logic Elements (LE) and Logic Array Blocks (LAB) chapter in the Cyclone III Device Handbook. 1–6 Cyclone III Device Handbook, Volume 1 Note (1) Altera Corporation-Preliminary Staggered I/O Ring Up to 288 Embedded Multipliers for High-Throughput DSP Up to 119,088 ...
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... Cyclone III devices offer up to 288 embedded multiplier blocks and support the following modes: one individual 18-bit x18-bit multiplier per block, or two individual 9-bit x 9-bit multipliers per block. The Quartus II software includes megafunctions that are used to control the mode of Altera Corporation-Preliminary March 2007 Cyclone III Device Architecture Port Width Configuration ...
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... Suite of common video and image processing functions ● Complete reference designs for end-market applications DSP Builder interface tool between The MathWorks Simulink ® MATLAB design environment, and Quartus II software DSP development kits ® and Altera Corporation-Preliminary March 2007 ...
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... PLLs can be used for device clock management, external system clock management, and I/O interfaces. Cyclone III PLLs can be dynamically reconfigured to enable auto-calibration of external memory interfaces while the device is in operation. This feature also enables support of multiple input source Altera Corporation-Preliminary March 2007 Note (1) I/O Standard ● ...
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... Cyclone III PLL dynamic reconfiguration feature to calibrate over process, voltage and temperature changes. f For more information, refer to the External Memory Interfaces chapter in the Cyclone III Device Handbook. 1–10 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
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... Cyclone III devices use SRAM cells to store configuration data. Configuration data is downloaded to Cyclone III devices each time the device powers up. Low-cost configuration options include Altera EPCS family serial flash devices, as well as parallel flash configuration options using commodity Intel and Spansion devices. These options provide flexibility for general-purpose applications and the ability to meet ® ...
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... V devices. The Cyclone III devices hot socketing feature eliminates power-up sequence requirements for other devices on the board for proper FPGA operation. f For more information, refer to the Hot Socketing and Power-On Reset chapter in the Cyclone III Device Handbook. 1–12 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
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... For more information, refer to IEEE 1149.1 (JTAG) Boundary-Scan Testing chapter in the Cyclone III Device Handbook. Reference and Figure 1–2 Ordering Information Altera Corporation-Preliminary March 2007 Reference and Ordering Information describes the ordering codes for Cyclone III devices. Cyclone III Device Handbook, Volume 1 1–13 ...
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... Number of pins for a particular package: 144 240 256 324 484 780 shows the revision history for this document. Changes Mode Initial Release Optional Suffix Engineering sample Speed Grade Operating Temperature ˚ ˚ ˚ ˚ Industrial temperature ( 100 C) J Summary of Changes Altera Corporation-Preliminary March 2007 ...
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... Each LE features: ■ ■ ■ ■ ■ ■ ■ Figure 2–1 Altera Corporation-Preliminary March 2007 2. Logic Elements and Logic Array Blocks in Cyclone III ® III devices. A four-input look-up table (LUT), which can implement any function of four variables A programmable register A carry chain connection ...
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... Asynchronous Chip-Wide Clear Logic Reset (DEV_CLRn) Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Register Bypass Row, Column, And Direct Link D Q Routing ENA CLRN Row, Column, And Direct Link Routing Local Routing Register Chain Output Altera Corporation-Preliminary March 2007 ...
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... LUTs to be used for combinational functions and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. Figure 2–2 Altera Corporation-Preliminary March 2007 shows a register cascading among LEs in Cyclone III. Cyclone III Device Handbook, Volume 1 Logic Elements “ ...
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... LE carry-in. LE carry chains can span more than 16 LEs by using the LAB carry-in and LAB carry-out. 2–4 Cyclone III Device Handbook, Volume 1 To general or local routing Register chain output To general or local routing Register chain output To general or local routing Register chain output Figure 2–3 shows LE carry chains. Altera Corporation-Preliminary March 2007 ...
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... If required, you can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Altera Corporation-Preliminary March 2007 data1 data2 (in from cout ...
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... Wide) aclr (LAB Wide) Register Bypass Register Feedback Figure 2–4). The Row, Column, and Q Direct Link Routing D Row, Column, and ENA Direct Link Routing CLRN Local Routing Register Chain Output (Figure 2–5). LEs in arithmetic mode Altera Corporation-Preliminary March 2007 ...
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... M9K memory block through the direct link interconnect. Whereas if the carry chains ran horizontally, any LAB not next to the column of M9K memory blocks would use other row or column interconnects to drive a M9K memory block. A carry chain continues as far as a full column. Altera Corporation-Preliminary March 2007 Register chain sload sclear ...
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... Cyclone III Device Handbook, Volume 1 16 LEs LAB control signals LE carry chains Register chains Local interconnect shows the Cyclone III LAB. Local Interconnect LAB Row Interconnect Column Interconnect Direct link interconnect from adjacent block Direct link interconnect to adjacent block Altera Corporation-Preliminary March 2007 ...
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... You may use up to eight control signals at a time. Register packing and the synchronous load cannot be used simultaneously. Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals. Altera Corporation-Preliminary March 2007 shows the direct link connection. Local ...
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... NOT gate push-back technique. Cyclone III devices can only support either a preset or asynchronous clear signal. 2–10 Cyclone III Device Handbook, Volume 1 Figure 2–8 shows the LAB control signal generation circuit. labclkena2 labclkena1 labclk1 labclk2 labclr1 synclr syncload labclr2 Altera Corporation-Preliminary March 2007 ...
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... LEs and LABs. Document Table 2–1 Revision History Table 2–1. Document Revision History Date and Document Version March 2007 v1.0 Altera Corporation-Preliminary March 2007 shows the revision history for this document. Changes Made Initial Release Cyclone III Device Handbook, Volume 1 Conclusion Summary of Changes 2– ...
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... Logic Elements and Logic Array Blocks in Cyclone III Devices 2–12 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
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... The MultiTrack interconnect consists of row (direct link, R4, and R24) and column (register chain, C4, and C16) interconnects that span fixed distances. A routing structure with fixed-length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Altera Corporation-Preliminary March 2007 3. MultiTrack Interconnect in Cyclone III Devices ® ...
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... Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 interconnects for high-speed access across the length of the device Figure 3–1 shows R4 interconnect connections from a Figure 3–1) can drive a given R4 interconnect. For R4 interconnects Altera Corporation-Preliminary March 2007 ...
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... LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, M9K memory blocks, embedded multipliers, and row and column I/O elements. These column resources include: ■ ■ ■ Altera Corporation-Preliminary March 2007 Notes (1), (2), (3) Adjacent LAB can Drive onto Another ...
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... Cyclone III Device Handbook, Volume 1 Figure 3–2 shows the register chain interconnects. Local Interconnect Routing Among LEs in the LAB LE 1 Carry Chain Routing to Adjacent ALM LE 2 Local LE 3 Interconnect Altera Corporation-Preliminary ® II compiler Register Chain Routing to Adjacent LE's Register Input March 2007 ...
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... LABs or blocks (see Figure range and drive blocks to the left or right for column-to-column connections. Altera Corporation-Preliminary March 2007 Figure 3–3 shows the C4 interconnect connections from a 3–3). The C4 interconnects can drive both blocks to extend their ...
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... Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect 3–6 Cyclone III Device Handbook, Volume 1 Notes (1), (2) Primary Local LAB Interconnect C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB LAB Neighbor C4 Interconnect Driving Down Altera Corporation-Preliminary March 2007 ...
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... Register Chain Local Interconnect v Direct Link Interconnect v R4 Interconnect R24 Interconnect v C4 Interconnect C16 Interconnect M9K Memory Block v Embedded Multipliers Column I/O Element Row I/O Element Altera Corporation-Preliminary March 2007 shows the Cyclone III device routing scheme. Destination Direct R4 R24 C4 C16 Link ...
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... Cyclone III LABs and LEs. 3–8 Cyclone III Device Handbook, Volume 1 shows the direct link connection. Local Direct link interconnect from right LAB, M9K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect to right LAB Altera Corporation-Preliminary March 2007 ...
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... M9K RAM Block Local Interconnect Region f See the Embedded Memory Blocks in Cyclone III Devices Chapter in volume 1 of the Cyclone III Device Handbook for more information about Cyclone III embedded memory blocks. Altera Corporation-Preliminary March 2007 dataout M9K RAM Block Byte enable ...
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... Direct Link Outputs to Adjacent LABs R4 Interconnects Embedded Multiplier Control 36 [35..0] [35..0] 18 Row Interface Block 36 Inputs per Row 36 Outputs per Row Direct Link Interconnect from Adjacent LAB 36 LAB 18 18 LAB Block Interconect Region C4 Interconnects Altera Corporation-Preliminary March 2007 ...
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... Document Revision History Table 3–2. Document Revision History Date and Document Version March 2007 v1.0 Initial Release Altera Corporation-Preliminary March 2007 signa signb clk clkena aclr Changes Made Cyclone III Device Handbook, Volume 1 Conclusion Summary of Changes 3– ...
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... MultiTrack Interconnect in Cyclone III Devices 3–12 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
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... CIII51005-1.0 Introduction Cyclone on-chip memory needs of Altera embedded memory structure consists of columns of M9K memory blocks that you can configure to provide various memory functions, such as RAM, shift registers, ROM, and first-in first-out (FIFO) buffers. M9K memory blocks provide up to 3.98 Mbit of RAM at a maximum of 260 MHz for synchronous operation (see bits-per-density) ...
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... Outputs cleared Read address registers and output registers only Output latches only Write and Read: Rising clock edges Outputs set to “Old Data” or “New Data” Outputs set to “Old Data” or “Don’t Care” Altera Corporation-Preliminary March 2007 ...
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... The read-enable (rden) and write-enable (wren) control signals control the read and write operations for each port of the memory blocks. You can disable read-enable or write-enable signals independently to save power whenever the operation is not required. Altera Corporation-Preliminary March 2007 shows the capacity and distribution of the M9K memory blocks Device ...
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... RAM block's write operations. The default value for the byte-enable signals is high 4–4 Cyclone III Device Handbook, Volume 1 clocken_b rden_b wren_b rden_a wren_a clocken_a addressstall_b aclr_b byteena_b aclr_a addressstall_a byteena_a Altera Corporation-Preliminary March 2007 ...
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... Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active high. selection. Table 4–3. Byte Enable for Cyclone III M9K Blocks byteena[3..0] Note to (1) Altera Corporation-Preliminary March 2007 datain×16 datain×18 [ [7..0] [8..0] [ [15 ...
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... Each of the two independent block sizes is less than or equal to half of the M9K block size. The maximum data width for each independent block is 18-bits wide. Each of the single-port memory blocks is configured in single-clock mode XXXX XX FFCD ABCD ABFF FFCD ABCD ® II software. It can Altera Corporation-Preliminary March 2007 ...
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... The default value for the address clock enable signals is low (disabled). the address clock enable waveforms during read and write cycles, respectively. Altera Corporation-Preliminary March 2007 “Single-Port Mode” on page 4–10 for more information. shows an address clock enable block diagram. The address ...
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... XX contents at a0 contents contents at a2 contents at a3 contents at a4 contents at a5 4–8 Cyclone III Device Handbook, Volume dout0 doutn dout1 dout0 dout1 dout1 dout4 dout1 dout1 dout1 dout4 dout5 Altera Corporation-Preliminary March 2007 ...
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... There are three ways to reset registers in the M9K blocks: power up the device, use the aclr signal for output register only, or assert the device-wide reset signal using the DEV_CLRn option. Altera Corporation-Preliminary March 2007 for details on the different widths Asserting asynchronous clear to the read address register duringa read operation could corrupt the memory content ...
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... Figure 4–7 shows the single-port memory (2) data[ ] address[ ] wren byteena[] addressstall inclock inclocken rden aclr Figure 4–7: You can implement two single-port memory blocks in a single M9K block. See “Packed Mode Support” for more details. q[] outclock outclocken Altera Corporation-Preliminary March 2007 ...
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... Figure 4–8. Cyclone III Single-Port Mode Timing Waveforms clk_a wren_a rden_a address_a data_a q_a (old data) q_a (new data) Altera Corporation-Preliminary March 2007 “Read-During-Write Operations” on page 4–28 8192 × 1 4096 × 2 2048 × 4 1024 × 8 1024 × 9 512 × 16 512 × ...
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... Figure 4–9: Simple dual-port RAM supports input/output clock mode in addition to the read/write clock mode shown. Write Port 256 × (1) rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken Table 4–4 shows 1024 × 9 512 × 18 256 × Altera Corporation-Preliminary March 2007 ...
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... True dual-port mode supports any combination of two-port operations: two reads, two writes, or one read and one write, at two different clock frequencies. configuration. Altera Corporation-Preliminary March 2007 for more details about this behavior. shows timing waveforms for read and write operations in a0 ...
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... M9K block mixed-port width configurations. Write Port 2048 × 4 1024 × for more details on this behavior. (1) data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b clocken_b rden_b aclr_b q_b[] 512 × 16 1024 × 9 512 × “Read-During-Write Altera Corporation-Preliminary March 2007 ...
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... The size shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n), and must be less than or equal to the maximum number of memory bits, which is Altera Corporation-Preliminary March 2007 shows true dual-port timing waveforms for the write a0 ...
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... Figure 4–13. Cyclone III Shift Register Mode Configuration w × m × n Shift Register m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W 4–16 Cyclone III Device Handbook, Volume 1 shows the Cyclone III memory block in the shift register Number of Taps W W Altera Corporation-Preliminary March 2007 ...
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... FIFO buffer. f Refer to the Single- and Dual-Clock FIFO Megafunctions User Guide for more information on FIFO buffers. You will find this at the Altera web site at http://www.altera.com/literature/ug/ug_fifo.pdf. Clocking Modes Cyclone III M9K memory blocks support the following clocking modes: ■ ...
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... A and port B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port also supports independent clock enables for port A and B registers. Figure 4–14 4–18 Cyclone III Device Handbook, Volume 1 shows a memory block in independent clock mode. Altera Corporation-Preliminary March 2007 ...
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... Figure 4–14. Cyclone III Memory Block in Independent Clock Mode Altera Corporation-Preliminary March 2007 Clocking Modes Cyclone III Device Handbook, Volume 1 4–19 ...
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... Figures clock mode for true dual-port, simple dual-port, and single-port modes, respectively. 4–20 Cyclone III Device Handbook, Volume 1 4–15, 4–16, and 4–17 show the memory block in input/output Altera Corporation-Preliminary March 2007 ...
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... Figure 4–15. Cyclone III Input/Output Clock Mode in True Dual-Port Mode Altera Corporation-Preliminary March 2007 Clocking Modes Cyclone III Device Handbook, Volume 1 4–21 ...
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... Read Address D Q ENA Data Out Byte Enable D Q ENA Write Address D Q ENA Read Address Clock Enable Write Address Clock Enable Read Enable Q D ENA Write Enable D Q ENA To MultiTrack Interconnect ( ENA Altera Corporation-Preliminary March 2007 ...
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... Similarly, a read clock controls the data outputs, read address, and read- enable registers. The memory blocks support independent clock enables for both the read and write clocks. read/write clock mode. Altera Corporation-Preliminary March 2007 Memory Block 256 ´ ...
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... Read Address D Q ENA Data Out Byte Enable D Q ENA Write Address D Q ENA Read Address Clock Enable Write Address Clock Enable Read Enable D Q ENA Write Enable D Q ENA To MultiTrack Interconnect ( ENA Altera Corporation-Preliminary March 2007 ...
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... In this mode, you can control all registers of the memory block with a single clock together with clock enable. Figures mode for true dual-port, simple dual-port, and single-port modes, respectively. Altera Corporation-Preliminary March 2007 4–19, 4–20, and 4–21 show the memory block in single-clock ...
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... Figure 4–19. Cyclone III Single-Clock Mode in True Dual-Port Mode Note to Figure 4–19: (1) See the Cyclone III Device Family Data Sheet in the Cyclone III Device Handbook, Volume 1, for more information on the MultiTrack interconnect. 4–26 Cyclone III Device Handbook, Volume 1 (1) Altera Corporation-Preliminary March 2007 ...
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... Note to Figure 4–20: (1) See the Cyclone III Device Family Data Sheet in the Cyclone III Device Handbook, Volume 1, for more information on the MultiTrack interconnect. Altera Corporation-Preliminary March 2007 Memory Block 256 ´ Data In 512 ´ 8 ENA 1,024 ´ 4 2,048 ´ ...
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... ENA 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 Address D Q ENA Data Out Byte Enable D Q ENA Address Clock Enable Read Enable D Q ENA Write Enable D Q ENA To MultiTrack Interconnect ( ENA and “Mixed-Port describe the functionality of the Altera Corporation-Preliminary March 2007 ...
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... Therefore, the output can be a combination of new and old data determined by byte enable. Figures 4–23 read-during-write behavior with both “New Data” and “Old Data” modes, respectively. Altera Corporation-Preliminary March 2007 shows the difference between these flows. Port B data in ...
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... RAM outputs to reflect the old data at that address location. In “Don't Care” mode, the same operation results in a "Don't Care" or unknown value on the RAM outputs. 4–30 Cyclone III Device Handbook, Volume a0(old data) a1(old data Altera Corporation-Preliminary March 2007 ...
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... Since there is no conflict resolution circuitry built into the memory blocks, this results in unknown data being written to that location. Therefore, you need to implement conflict-resolution logic external to the memory block. Altera Corporation-Preliminary March 2007 shows a sample functional waveform of mixed port a ...
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... For more information on MIF files, refer to the RAM Megafunction User Guide as well as the Quartus II Handbook. You will find these documents at the Altera web site at http://www.altera.com/literature/ug/ug_ram.pdf and http://www.altera.com/literature/lit-qts.jsp, respectively. Power Management Cyclone III memory block clock enables allow you to control clocking of each memory block to reduce AC power consumption ...
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... Table 4–7. Document Revision History Date and Document Version March 2007 v1.0 Initial Release Altera Corporation-Preliminary March 2007 Changes Made Cyclone III Device Handbook, Volume 1 Document Revision History Summary of Changes 4–33 ...
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... Memory Blocks in Cyclone III Devices 4–34 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
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... Video and image processing suite ● Complete reference designs for end market applications DSP Builder interface between the Mathworks Simulink and MATLAB design environment and the Altera DSP optimized development kits “Software Support” on page Cyclone III Devices ® ...
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... There is no restriction on the data width of the multiplier, but the greater the data width, the slower the multiplication process. Figure 5–1. Embedded Multipliers Arranged in Columns with Adjacent LABs 5–2 Cyclone III Device Handbook, Volume 1 Embedded Multiplier Column 1 LAB Embedded Row Multiplier Figure 5–1 shows one of the Altera Corporation-Preliminary March 2007 ...
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... Cyclone III devices using embedded multipliers and soft multipliers. Table 5–2. Number of Multipliers in Cyclone III Devices (Part EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 Altera Corporation-Preliminary March 2007 Embedded Device Multipliers Multipliers ...
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... The total number of multipliers may vary according to the multiplier mode you use. Multiplier stage Input and output registers Input and output interfaces shows the multiplier block architecture. Soft Multipliers Total Multipliers (16 × 16) (1) (2) 260 416 305 549 Altera Corporation-Preliminary March 2007 ...
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... Multiplier Stage The multiplier stage of an embedded multiplier block supports multipliers as well as other multipliers in between these configurations. Depending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel. Altera Corporation-Preliminary March 2007 signa signb aclr clock ...
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... When the signa and signb signals are unused, the Quartus II software sets the multiplier to perform unsigned multiplication by default. clock clock enable asynchronous clear for multiplier details. Table 5–3 shows the sign of the Result Logic Level Low Unsigned High Signed Low Signed High Signed Altera Corporation-Preliminary March 2007 ...
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... Multipliers You can configure each embedded multiplier to support a single multiplier for input widths bits. embedded multiplier configured to support an 18-bit multiplier. Altera Corporation-Preliminary March 2007 One 18-bit multiplier Up to two 9-bit independent multipliers You can also use the Cyclone III embedded multipliers to ...
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... Cyclone III Device Handbook, Volume 1 signa signb aclr clock ena D Q ENA D Q CLRN ENA CLRN D Q ENA CLRN 18 × 18 Multiplier Embedded Multiplier Data Out [35..0] Figure 5–4 shows Altera Corporation-Preliminary March 2007 ...
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... Therefore, all of the data A inputs feeding the same embedded multiplier must have the same sign representation. Similarly, all of the data B inputs feeding the same embedded multiplier must have the same sign representation. Altera Corporation-Preliminary March 2007 signa signb aclr ...
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... Embedded Multipliers in Cyclone III Devices Software Altera provides two methods for implementing multipliers in your design using embedded multiplier resources: instantiation and inference. Support Both methods use the following four Quartus II megafunctions: ■ ■ ■ ■ In the first method, you can use the lpm_mult, altmult_add, and altfp_mult megafunctions to implement multipliers ...
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... Document Table 5–4 Revision History Table 5–4. Document Revision History Date & Document Version March 2007 v1.0 Initial Release Altera Corporation-Preliminary March 2007 shows the revision history for this document. Changes Made Cyclone III Device Handbook, Volume 1 Conclusion Summary of Changes 5–11 ...
Page 100
... Embedded Multipliers in Cyclone III Devices 5–12 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
Page 101
... The larger devices (EP3C16 devices and larger) support four dedicated clock pins on each side of the device. These clock pins can drive 20 global clock networks. Altera Corporation-Preliminary March 2007 6. Clock Networks and PLLs in Cyclone III Devices ® ...
Page 102
... Cyclone III Device Handbook, Volume 1 shows the number of global clocks available across the Device EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 Number of Global Clocks Altera Corporation- Preliminary March 2007 ...
Page 103
... CLK13 DIFFCLK_7p / CLK14 DIFFCLK_6n / CLK15 DIFFCLK_6p / v PLL1_c0 (1) v PLL1_c1 ( PLL1_c2 (1) v PLL1_c3 (1) v PLL1_c4 (1) PLL2_c0 (1) PLL2_c1 (1) PLL2_c2 (1) PLL2_c3 (1) PLL2_c4 (1) PLL3_c0 PLL3_c1 Altera Corporation-Preliminary March 2007 shows the connectivity of the clock sources to the global Global Clock Networks EP3C16 through EP3C80 Devices Only ...
Page 104
... CDPCLK0 or CDPCLK7 (3) DPCLK2 (2) CDPCLK1 CDPCLK2 (3) DPCLK5 (2) DPCLK7 (3) DPCLK4 (2) DPCLK6 (3) DPCLK6 (2) DPCLK5 DPCLK6 (3) DPCLK3 (2) CDPCLK4 or CDPCLK3 (3) DPCLK8 DPCLK11 DPCLK9 DPCLK10 DPCLK5 DPCLK2 DPCLK4 6–4 Cyclone III Device Handbook, Volume 1 Global Clock Networks EP3C16 through EP3C80 Devices Only Altera Corporation- Preliminary March 2007 v v ...
Page 105
... However, when using them as general-purpose input pins, they do not have support for an I/O register and must use LE-based registers in place of an I/O register. Altera Corporation-Preliminary March 2007 Global Clock Networks EP3C16 through EP3C80 Devices Only ...
Page 106
... Elements) to drive a high fan-out, low skew signal path. Clock control blocks which have inputs driven by internal logic will not be able to drive PLL inputs. Description CDPCLK I/O pins are bidirectional IRDY DQS signals for PCI, or for Altera Corporation- Preliminary March 2007 ...
Page 107
... Each PLL generates five clock outputs through the c[4..0] counters. Two of these clocks can drive the global clock network through a clock control block as shown in Altera Corporation-Preliminary March 2007 Dynamic global clock network clock source selection Global clock network power-down (dynamic enable and disable) shows the clock control block ...
Page 108
... GCLK[19..0] Clock Control Block ( CLK[15..12] DPCLK[3..2] DPCLK[5..4] pins in each corner can feed the clock control block at a time. The other Figure 6–2 and Note (1) CDPCLK6 PLL 2 CDPCLK5 ( DPCLK7 CLK[7..4] 4 DPCLK6 2 (2) CDPCLK4 5 PLL 4 CDPCLK3 CDPCLK Altera Corporation- Preliminary March 2007 ...
Page 109
... Two DPCLK pins and two CDPCLK pins from both the left and right sides and four DPCLK pins and two CDPCLK pins from both the top and bottom ■ Five signals from internal logic Altera Corporation-Preliminary March 2007 DPCLK6 GCLK[9.. ...
Page 110
... DPCLK 5 Five Clock Control Blocks on Each Side of the Device Figure 6–4: The left and right sides of the device have two DPCLK bottom of the device have four Figure 6–1. 5 GCLK DPCLK pins, and the top and pins. Altera Corporation- Preliminary March 2007 ...
Page 111
... In addition, the PLL can remain locked independent of the clkena signals since the loop- related counters are not affected. Figure 6–5. Clkena Implementation Altera Corporation-Preliminary March 2007 Figure 6–1 on page shows how to implement clkena. This allows you to gate off ...
Page 112
... Figure 6–6. Clkena Implementation - Output Enable clkin clkena clk_out The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization. Altera recommends using the clkena signals when switching the clock source to the PLLs or the global clock network. The recommended sequence is ...
Page 113
... Hardware Features C (output counters counter sizes Dedicated clock outputs Clock input pins Spread-spectrum input clock tracking PLL Cascading Compensation modes Phase shift resolution Programmable duty cycle Output counter cascading Input clock Switchover User mode reconfiguration Altera Corporation-Preliminary March 2007 Device PLL1 PLL ...
Page 114
... Smaller degree increments are possible depending on the frequency and divide parameters. Figure 6–7 6–14 Cyclone III Device Handbook, Volume 1 Yes shows the location of PLLs in Cyclone III devices. Availability Altera Corporation- Preliminary March 2007 ...
Page 115
... Figure 6–7: (1) This figure shows the PLL and clock inputs in the EP3C16 through EP3C120 devices. The EP3C5 and EP3C10 devices have only eight global clock input pins (CLK[0..3] and CLK[4..7]) and PLLs 1 and 2. Altera Corporation-Preliminary March 2007 Note (1) CLK[8..11] I/O Bank 8 I/O Bank 7 GCLK[10 ...
Page 116
... Cyclone III Device Handbook, Volume the PFD is equal to the input clock (f that is applied to the other input of the PFD. REF ) is equal VCO ). The input reference clock REF ) divided by the pre-scale IN ) applied to one input of the FB Altera Corporation- Preliminary March 2007 ...
Page 117
... Notes to Figure 6–8: (1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL. (2) This is the VCO post-scale counter, K. Altera Corporation-Preliminary March 2007 shows a simplified block diagram of the major components of (1), (2) lock LOCK circuit ÷ ...
Page 118
... I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, differential HSTL, and differential SSTL. 6–18 Cyclone III Device Handbook, Volume 1 Notes (1), ( PLL # C3 C4 (1) clkena 0 (2) PLL #_CLKOUTp PLL #_CLKOUTn Figure 6–9. (1) clkena 1 (2) Altera Corporation- Preliminary March 2007 ...
Page 119
... PLL or a pin-driven dedicated global clock. An internally generated global signal cannot drive the PLL. (2) You can drive to global clock network (C[4..0]) or dedicated external clock output pins (only C0). Altera Corporation-Preliminary March 2007 Figure 6–10 shows the Cyclone III PLL ports as named in the ...
Page 120
... PLL switchover circuit Logic array General PLL control signal Logic array PFD Source Destination PLL counter Internal or external clock (only c0) PLL switch- Logic array over circuit PLL lock detect Logic array PLL clock Logic array multiplexer Altera Corporation- Preliminary March 2007 ...
Page 121
... I/O standard is used. Figure 6–11. Phase Relationship Between Clock and Data in Source-Synchronous Mode Altera Corporation-Preliminary March 2007 The input/output delays are fully compensated by the PLL only when using the dedicated clock input pins associated with a given PLL as the clock sources ...
Page 122
... Quartus II software for all data pins clocked by a source-synchronous mode PLL. Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II software. Figure 6–12 shows a waveform example of the phase Notes (1), (2) Altera Corporation- Preliminary March 2007 ...
Page 123
... When using this mode, you must use the same I/O standard on the input clock and output clocks in order to guarantee clock alignment at the input and output pins. Altera Corporation-Preliminary March 2007 shows a waveform example of the PLL clocks' phase Note (1) ...
Page 124
... There are five generic post-scale counters per PLL 6–24 Cyclone III Device Handbook, Volume 1 shows an example waveform of the PLL clocks' phase Phase Aligned (m/n). Each output port has a in Altera Corporation- Preliminary March 2007 ...
Page 125
... When cascading counters to implement a larger division of the high- frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings. For example and then the cascaded value is C0 × Altera Corporation-Preliminary March 2007 6–15. VCO Output VCO Output ...
Page 126
... When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is then set back to its nominal setting. When driven low again, the PLL resynchronizes to its input as it re-locks. 6–26 Cyclone III Device Handbook, Volume 1 Altera Corporation- Preliminary March 2007 ...
Page 127
... If the input clock to the PLL is toggling or unstable upon power up, assert the areset signal after the input clock is stable and within specifications. Altera recommends that you use the areset and locked signals in your designs to control and observe the status of your PLL. Cyclone III Device Handbook, Volume 1 Hardware Features 6– ...
Page 128
... Activeclock clkswitch Provides manual switchover support PFD fbclk Figure 6–16. In this case, Altera Corporation- Preliminary March 2007 ...
Page 129
... Also, because the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clksw signal to switch to inclk1. Altera Corporation-Preliminary March 2007 Use the clkswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies ...
Page 130
... PLL reference. This is also when the activeclock signal changes to indicate which clock is currently feeding the PLL. 6–30 Cyclone III Device Handbook, Volume 1 Note (1) (1) shows an example of a waveform illustrating the switchover Altera Corporation- Preliminary March 2007 ...
Page 131
... When the clkswitch signal goes high, the switchover sequence starts. The falling edge of the clkswitch signal does not cause the circuit to switch back to the previous input clock. Altera Corporation-Preliminary March 2007 Hardware Features Cyclone III Device Handbook, Volume 1 ...
Page 132
... VCO frequency gradually decreases when the primary clock is lost and then increases as the VCO locks on to the secondary clock. After the VCO locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency. Altera Corporation- Preliminary March 2007 ...
Page 133
... The minimum delay time that you can insert using this method is defined by: Φ fine where f Altera Corporation-Preliminary March 2007 Disable the system during switchover not tolerant to frequency variations during the PLL resynchronization period. You can use the clkbad[0] and clkbad[1] status signals to turn off the PFD (pfdena = 0) so the VCO maintains its last frequency ...
Page 134
... The PLL operating frequency defines this phase fine = C-1/f = (C-1)N/Mf vco ref shows an example of phase shift insertion using the fine ° phase from the VCO and has the C value for the counter set to = 800 MHz VCO . fine (two complete VCO coarse Altera Corporation- Preliminary March 2007 ...
Page 135
... Two PLLs may be cascaded to each other through the clock network. If the design cascades PLLs, the source (upstream) PLL should have a high-bandwidth setting, while the destination (downstream) PLL should have a low-bandwidth setting. cascading PLLs. Altera Corporation-Preliminary March 2007 PLL Cascading Figure 6–21 shows usage of GCLK while Cyclone III Device Handbook, Volume 1 6– ...
Page 136
... Note (1) Five Clock Control Blocks Input to PLL CLK[8..11 GCLK[10..14] GCLK[0:19] GCLK[0:19] GCLK[0:19] 20 GCLK[15..19 CLK[12..15] Five Clock Control Blocks PLL 2 2 Output from PLL 5 2 Five Clock Control Blocks CLK[4..7] GCLK[5..9] 2 PLL 5 4 Output from PLL Altera Corporation- Preliminary March 2007 ...
Page 137
... The maximum scanclk frequency is 100 MHz. After shifting the last bit of data, asserting the configupdate signal for at least one scanclk clock cycle synchronously updates the PLL configuration bits with the data in the scan registers. Altera Corporation-Preliminary March 2007 Pre-scale counter (n) Feedback counter (m) ...
Page 138
... I/O pins circuit PLL reconfiguration or I/O pins circuit Logic array PLL reconfiguration or I/O pins circuit Logic array PLL reconfiguration or I/O pins circuit PLL Logic array or I/O reconfig. pins circuit PLL Logic array or I/O reconfig. pins circuit Altera Corporation- Preliminary March 2007 ...
Page 139
... SCANCLKENA Dn_old SCANDATAOUT CONFIGUPDATE SCANDONE ARESET Altera Corporation-Preliminary March 2007 The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the first bit of scandata (Dn). Serial data (scandata) is shifted into the scan chain on the 2 rising edge of scanclk. After all 144 bits have been scanned into the scan chain, the scanclkena signal is de-asserted to prevent inadvertent shifting of bits in the scan chain ...
Page 140
... High time count = 2 cycles Low time count = 1 cycle rselodd = 1 effectively equals: High time count = 1.5 cycles ● Low time count = 1.5 cycles ● Duty cycle = (1.5/3) % high time count and (1.5/3) % low time ● count Altera Corporation- Preliminary March 2007 ...
Page 141
... PLL. Table 6–9. Cyclone III PLL Reprogramming Bits Block Name Charge Pump Loop Filter Total number of bits Notes to (1) (2) (3) Altera Corporation-Preliminary March 2007 Number of Bits Counter ( (3) 9 Table 6–9: LSB bit for C4 low-count value is the first bit shifted into the scan chain. ...
Page 142
... Cyclone III PLLs. Figure 6–25. Scan Chain Bit Order 6–42 Cyclone III Device Handbook, Volume 1 shows the scan chain order of PLL components LSB C4 C3 shows the scan chain bit order sequence for one PLL post Altera Corporation- Preliminary March 2007 ...
Page 143
... Cyclone III PLLs. Table 6–10. Charge Pump Bit Control Table 6–11. Loop Filter Resistor Value Control LFR[4] LFR[ Table 6–12. Loop Filter Control of High Frequency Capacitor Altera Corporation-Preliminary March 2007 Table CP[2] CP[ LFR[2] LFR[ ...
Page 144
... VCO frequency at a time. The output clocks are active during this phase reconfiguration process. 6–44 Cyclone III Device Handbook, Volume 1 shows the settings for bypassing the counters in Cyclone III MSB ( PLL counter bypassed ( PLL counter not bypassed Description Altera Corporation- Preliminary March 2007 ...
Page 145
... PLL is ready to act on a possible second adjustment pulse. Asserts based on internal PLL timing. De-asserts on rising edge of Table 6–15 PHASECOUNTERSELECT setting: PHASECOUNTERSELECT [2] Altera Corporation-Preliminary March 2007 shows the control signals that are used for dynamic phase Description Logic array or I/O pins SCANCLK . ...
Page 146
... The phasestep pulses must be at least one scanclk cycle apart. Wait for phasedone to go low. De-assert phasestep. Wait for phasedone to go high. Repeat steps 1 through 5 as many times as required to get multiple phase shifts. 6–26, this is shown by the second scanclk falling edge. Altera Corporation- Preliminary March 2007 ...
Page 147
... VCCA<PLL number> and GNDA. Connect the VCCA power pin to a 2.5-V power supply, even if you do not use the PLL. Run a thick trace from the power supply to each VCCA pin. The traces should be at least 20 mils thick. Altera Corporation-Preliminary March 2007 Spread-Spectrum Clocking Cyclone III Device Handbook, Volume 1 ...
Page 148
... Cyclone III device. You can connect the GNDA pins directly to the same ground plane as the device's digital ground. 6–48 Cyclone III Device Handbook, Volume 1 Figure 6–27. Place a ferrite bead that exhibits high impedance at Altera Corporation- Preliminary March 2007 ...
Page 149
... PLL output frequencies and adjust the output clock phase shift dynamically. These PLLs are capable of offering flexible system-level clock management that Altera Corporation-Preliminary March 2007 Note (1) Ferrite Bead 10μ ...
Page 150
... Document Revision History Table 6–16. Document Revision History Date and Document Version March 2007 v1.0 Initial Release 6–50 Cyclone III Device Handbook, Volume 1 Changes Made Altera Corporation- Preliminary Summary of Changes March 2007 ...
Page 151
... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation-Preliminary Section II. I/O and External Chapter 7, Cyclone III Device I/O Features Chapter 8, High-Speed Differential Interfaces in Cyclone III Devices ...
Page 152
... I/O and External Memory Interfaces Section II–2 Preliminary Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary ...
Page 153
... Altera Corporation-Preliminary March 2007 7. Cyclone III Device I/O ® ® Quartus II software completes the solution with powerful pin Single-ended non-voltage-referenced and voltage-referenced I/O standards Differential I/O standards Output current strength control ...
Page 154
... There are two paths available for combinational or registered inputs to the logic array. Each path contains a unique programmable delay chain. 7–2 Cyclone III Device Handbook, Volume 1 shows the Cyclone III IOE structure. The IOE contains one OE Register Register D Q Output Register D Q Input Register D Output Register Altera Corporation-Preliminary March 2007 ...
Page 155
... I/O block connects to the logic array. f For more information on Cyclone III routing architecture, please refer to the MultiTrack Interconnect in Cyclone III Devices chapter in the Cyclone III Device Handbook. Altera Corporation-Preliminary March 2007 Cyclone III I/O Element Figure 7–2 shows how a Figures 7–3 and 7– ...
Page 156
... Cyclone III Device Handbook, Volume 1 C4 Interconnect I/O Block Local Interconnect 32 io_dataina[3..0] (2) io_datainb[3..0] Direct Link Interconnect from Adjacent LAB io_clk[5..0] 32 Data & Control Signals from Logic Array (1) Horizontal I/O Block Horizontal I/O Block Contains up to Four IOEs Altera Corporation-Preliminary March 2007 ...
Page 157
... The 32 data and control signals are used to support up to four IOEs per two column I/O blocks. Each of the four IOEs in the column I/O block can have two io_datain (combinational or registered) inputs. (2) Altera Corporation-Preliminary March 2007 Column I/O Block 32 IO_dataina[3:0] IO_datainb[3:0](2) ...
Page 158
... Each of the five IOEs in the column I/O block can have two io_datain (combinational or registered) inputs. (2) 7–6 Cyclone III Device Handbook, Volume 1 Column I/O Block IO_dataina[4:0] IO_datainb[4:0](2) LAB C16 Interconnect Column I/O Block Contains up to Four IOEs io_clk[5..0] LAB Altera Corporation-Preliminary March 2007 ...
Page 159
... LAB, dedicated I/O clocks, or column and row interconnects. All registers share sclr and aclr, but each register can individually disable sclr and aclr. Altera Corporation-Preliminary March 2007 ) provide a dedicated routing io_clk[5..0] Figure 7–5 illustrates the control signal selection ...
Page 160
... Output Register Pin Delay Current Strength Control D Q Open-Drain Out Slew Rate Control ENA ACLR /PRN Input Pin to Input Register Input Register Delay or Input Pin Logic Array Delay ENA ACLR /PRN Altera Corporation-Preliminary V CCIO V CCIO Programmable Pull-Up Resistor Bus Hold March 2007 ...
Page 161
... OL 1 Table 7–1. Programmable Current Strength 1.2-V LVCMOS 1.5-V LVCMOS 1.8-V LVTTL/LVCMOS Altera Corporation-Preliminary March 2007 shows the possible settings for the I/O standards with current of the corresponding I/O standard. When you use programmable current strength, on-chip series termination is not available. ...
Page 162
... HSTL-15 Class I HSTL-15 Class II HSTL-18 Class I HSTL-18 Class II SSTL-18 Class I SSTL-18 Class II 7–10 Cyclone III Device Handbook, Volume I/O Standard Top and Bottom I/O Pins ( ( (1) (Part Current Strength Setting (mA) Left and Right I/O Pins — — Altera Corporation-Preliminary March 2007 ...
Page 163
... Cyclone III devices provide an optional open-drain (equivalent to an open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write-enable signals) that can be asserted by multiple devices in your system. Altera Corporation-Preliminary March 2007 ...
Page 164
... Disable the bus-hold feature when the I/O pin is configured for differential signals. Bus-hold circuitry is not available on the dedicated clock pins. voltage level driven through the resistor and for the overdrive to prevent overdriving CCIO level of the output CCIO Altera Corporation-Preliminary March 2007 ...
Page 165
... If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can Altera Corporation-Preliminary March 2007 If you enable the programmable pull-up, the device cannot use the bus-hold feature. The programmable pull-up resistors are not supported on the dedicated configuration, Joint Test Action Group (JTAG), and dedicated clock pins ...
Page 166
... For more information about Cyclone III high-speed differential interface support, refer to High-Speed Differential Interfaces in the Cyclone III Devices chapter of the Cyclone III Device Handbook. 7–14 Cyclone III Device Handbook, Volume 1 Altera Corporation-Preliminary March 2007 ...
Page 167
... R I/O buffer impedance until they match (as shown in shown in make up the I/O buffer. Figure 7–7. Cyclone III On-Chip Series Termination With Calibration Altera Corporation-Preliminary March 2007 When using on-chip series termination, programmable current strength is not available. OCT with calibration ...
Page 168
... CCIO CCIOs I/O Bank 7 I/O Bank 4 and R pins can be used as regular I/Os only the bank where the Figure 7–8 I/O bank with calibration block I/O bank without calibration block Calibration block coverage and R pins. When you UP DN Altera Corporation-Preliminary March 2007 ...
Page 169
... When used with the output drivers, on-chip termination sets the output driver impedance Ω . Cyclone III devices also support I/O driver series termination (R Altera Corporation-Preliminary March 2007 lists the I/O standards that support impedance matching and ...
Page 170
... Cyclone III Device Handbook, Volume 1 V CCIO GND On Chip Series Termination without Calibration I/O Standard Row I shown is S Receiving Device p Table 7–4 lists the I/O Setting Column I/O Unit Ω 50 Ω 25 Ω 50 Ω 25 Ω 50 Ω 25 Ω 50 Ω 25 Altera Corporation-Preliminary March 2007 ...
Page 171
... Impedance matching is implemented using the capabilities of the output driver and is subject to a certain degree of variation, depending on the process, voltage, and temperature. f Refer to the DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook, for more information about tolerance specification. Altera Corporation-Preliminary March 2007 On-Chip Termination Support ...
Page 172
... JESD8-9A 2.5 V 2.5 V JESD815 1.8 V 1.8 V JESD815 1.8 V 1.8 V JESD8-6 1.8 V 1.8 V Table 7–5 summarizes the I/O Top and Bottom I/O Side I/O Pins Pins CLK, PLL_ User I/O CLK, User I/O DQS OUT Pins DQS Altera Corporation-Preliminary March 2007 Pins ...
Page 173
... Differential HSTL-15 Class I (2) or Class II Differential Differential JESD8-16A HSTL-12 Class I (2) or Class II PPDS (3) Differential LVDS Differential RSDS and Differential (3) mini-LVDS Altera Corporation-Preliminary March 2007 V Level CCIO Standard Support Input Output JESD8-6 1.8 V 1.8 V JESD8-6 1.5 V 1.5 V JESD8-6 1.5 V 1.5 V JESD8-16a 1 ...
Page 174
... LVCMOS 1.2-V LVCMOS 3.0-V PCI and PCI-X ) and a termination voltage (V Figures 7–10 and 7–11. Top and Bottom I/O Side I/O Pins Pins PLL_ User I/O CLK, User I/O OUT Pins DQS Pins The reference voltage of the TT Altera Corporation-Preliminary March 2007 ...
Page 175
... Figure 7–10. Cyclone III HSTL I/O Standard Termination HSTL Class I Termination External On-Board Termination 50 Ω Transmitter Cyclone III Series OCT 50 Ω OCT With and Without Calibration Transmitter Altera Corporation-Preliminary March 2007 Ω V REF Transmitter Receiver V TT Cyclone III Series OCT 25 Ω 50 Ω 50 Ω V REF Transmitter ...
Page 176
... Cyclone III Device Handbook, Volume Ω 50 Ω V REF Transmitter Receiver Cyclone III V TT Series OCT 25 Ω 50 Ω 50 Ω V REF Receiver Transmitter SSTL Class Ω 50 Ω 25 Ω 50 Ω V REF Receiver Ω 50 Ω 50 Ω V REF Receiver Figures 7–12 Altera Corporation-Preliminary March 2007 ...
Page 177
... Termination 50 Ω External 50 Ω On-Board Termination 50 Ω Transmitter Cyclone III 50 Ω 50 Ω 50 Ω Series OCT 50 Ω 50 Ω OCT Transmitter Altera Corporation-Preliminary March 2007 Ω Receiver Transmitter Cyclone III Series OCT 25 Ω Transmitter Receiver Termination Scheme for I/O Standards Differential HSTL Class II ...
Page 178
... Cyclone III Device Handbook, Volume 1 Differential SSTL Class Ω Transmitter Receiver Cyclone III 50 Ω Series OCT 25 Ω Transmitter Receiver Figure Ω 50 Ω 50 Ω 50 Ω 25 Ω 50 Ω 25 Ω 50 Ω Receiver Ω 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω Receiver 7–14. Each device I/O pin is Altera Corporation-Preliminary March 2007 ...
Page 179
... PLL output clock pins. (6) The differential HSTL-12 I/O standards is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 class II is only supported in column I/O banks and 8 only. Altera Corporation-Preliminary March 2007 (1) I/O Bank 7 All I/O Banks Support: 3 ...
Page 180
... I/O standards supported when a pin is used as a regular I/O Standard (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (3) (3) ( (2) (3) (3) I/O Banks (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (3) (3) (3) (3) ( (3) (3) (3) (3) (3) Altera Corporation-Preliminary March 2007 (1) (1) (1) (1) (1) (3) v (3) ...
Page 181
... I/O pins. However, they will have slightly higher pin capacitance than regular user I/O pins when used with regular user I/O pins. summarizes the number of V Table 7–7. Number of V Device EP3C5 EP3C10 EP3C16 EP3C25 Altera Corporation-Preliminary March 2007 I/O Standard 1 2 (4) (4) Table 7–6: ...
Page 182
... LVTTL inputs and CCIO and a compatible V value. For example, if you choose to REF CCIO set to 1.25 V. I/O Banks pins. Any single I/O bank CCIO voltage per I/O bank, CCIO values—must REF set to 2.5 V and the CCIO Altera Corporation-Preliminary March 2007 ...
Page 183
... Corporation. Cyclone III devices meet the National Semiconductor Corporation PPDS Interface Specification and support the PPDS standard for outputs only. All the I/O banks of Cyclone III devices support the PPDS standard for output pins only. Altera Corporation-Preliminary March 2007 shows the acceptable input and output levels with (3) 2 ...
Page 184
... I/O pads in relation to differential pads. Use the following guidelines for placing single-ended pads with respect to differential pads and for differential output pads placement in Cyclone III devices. 7–32 Cyclone III Device Handbook, Volume 1 supply, there are CCIO Altera Corporation-Preliminary March 2007 ...
Page 185
... For the PPDS I/O standard: ■ ■ ■ ■ 1 Altera Corporation-Preliminary March 2007 Single-ended inputs can be no closer than four pads away from an LVDS I/O pad. Single-ended outputs can be no closer than five pads away from an LVDS I/O pad. A maximum of four 160-MHz LVDS output channels per V ground pair in column I/O banks ...
Page 186
... QFP packages. Any non-SSTL and non-HSTL output can be no closer than two pads away from a V Altera recommends that any SSTL or HSTL output, except for pintable defined DQ and DQS outputs (when used for DDR/DDR2/QDRII applications closer than two pads away from a V maintain acceptable noise levels. See page 7– ...
Page 187
... Package Type FineLine BGA QFP When at least one additional voltage referenced input and no other outputs exist in the same V applies in addition to the input and output limitations. See the following equations: Altera Corporation-Preliminary March 2007 REF pad) for QFP packages applies. REF Table 7–9. ...
Page 188
... Total number of bidirectional pads + total number of input pads for Fineline BGA packages Total number of bidirectional pads + total number of input pads for QFP packages Inputs Exist) REF Formula VCCIO and VCCIO and Table 7–11. Outputs REF Formula V CCIO V CCIO ≤ 32 ≤ 21 Altera Corporation-Preliminary March 2007 ...
Page 189
... DC Guidelines There is a current limit of 240 mA per twelve consecutive output top and bottom pins per power pair, as shown by the following equation: pin+11 Altera Corporation-Preliminary March 2007 7–12, depending on the package type. (Total number of bidirectional pads) + (Total number of output pads) ≤ 9 (per Total number of bidirectional pads + Total number of output pads ≤ ...
Page 190
... In all the cases listed above, the Quartus II software generates an error message for illegally placed pads. The I programmable current strength and is the same as the current strength as set in the Quartus II software. shows the revision history for this document. Changes Made varies with PIN Summary of Changes Altera Corporation-Preliminary March 2007 ...
Page 191
... The PPDS standard is the next generation of the RSDS standard introduced by National Semiconductor Corporation. PPDS technology was introduced to address the requirements for liquid crystal display (LCD) television interfaces to improve display performance. PPDS applications include multi-function LCD monitor and high-performance Altera Corporation-Preliminary March 2007 8. High-Speed Differential Interfaces in Cyclone III ® ...
Page 192
... In these cases, a power pin is located between the p and n pins. f Refer to the pin tables on the Altera web site at www.altera.com for more details on the location of the dedicated differential pins. Table 8–1 standards. ...
Page 193
... The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported on output pins. (4) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on dedicated clock input pins and PLL output clock pins. Altera Corporation-Preliminary March 2007 I/O banks 7 & 8 also support the HSTL-12 Class II I/O standard I/O Bank 8 ...
Page 194
... Refer to the pin tables on the Altera web site (www.altera.com) for details on the location of these pins. ...
Page 195
... EP3C25 FBGA FBGA EQFP FBGA EP3C40 FBGA FBGA FBGA EP3C55 FBGA FBGA EP3C80 FBGA Altera Corporation-Preliminary March 2007 Cyclone III High-Speed I/O Interface shows the numbers of Cyclone III device differential channels. (2) Number of Differential Channels Pin Count User I/O 144 16 256 62 144 16 ...
Page 196
... The maximum VOD for ANSI specification is 450 mV. The input voltage range can be reduced to the range of 1 1 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644 specification supports an input voltage range 2.4 V. (2) Number of Differential Channels Clock Pin Altera Corporation-Preliminary March 2007 Total 102 229 ...
Page 197
... I/O banks. with external resistor network on the top and bottom I/O banks. Figure 8–3. LVDS Interface with Dedicated Output Buffer on the Left and Right I/O Banks Altera Corporation-Preliminary March 2007 shows a simple point-to-point LVDS application using a Cyclone III Device ...
Page 198
... MHz. 8–8 Cyclone III Device Handbook, Volume 1 Resistor Network Ω Ω shows the signaling level for LVDS transmitter outputs and the negative channel ( LVDS Receiver 100 Ω Positive Channel ( Negative Channel ( Ground − Altera Corporation-Preliminary March 2007 ...
Page 199
... See the Cyclone III Device Datasheet: DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook for the RSDS I/O standard electrical specifications. Altera Corporation-Preliminary March 2007 High-Speed I/O Standards Support shows the signaling level for LVDS receiver inputs. Positive Channel ( ...
Page 200
... Cyclone III Device Handbook, Volume 1 shows the RSDS transmitter output signal waveforms. Positive Channel ( Negative Channel ( Ground − and the negative channel ( Figure 8–8 shows the RSDS I/O interface with a dedicated Figure 8–9. 50 Ω 100 Ω 50 Ω RSDS Receiver Altera Corporation-Preliminary March 2007 ...