EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 376

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
IEEE Std. 1149.1
BST Architecture
14–2
Cyclone III Device Handbook, Volume 1
TDI
TDO
TMS
TCK
Table 14–1. IEEE Std. 1149.1 Pin Descriptions
Pin
f
Test data input
Test data output
Test mode select
Test clock input
Description
■
■
■
■
In addition to BST, you can use the IEEE Std. 1149.1 controller for Cyclone
III device in-circuit reconfiguration (ICR). However, this chapter only
discusses the BST feature of the IEEE Std. 1149.1 circuitry.
For information on configuring Cyclone III devices via the IEEE Std.
1149.1 circuitry, refer to the Configuring Cyclone III Devices chapter in the
Cyclone III Device Handbook.
A Cyclone III device operating in IEEE Std. 1149.1 BST mode uses four
required pins, TDI, TDO, TMS and TCK. The TCK pin has an internal weak
pull-down resistor, while the TDI and TMS pins have weak internal
pull-up resistors. The TDO output pin and all the JTAG input pins are
powered by the 2.5-V/3.0-V V
during JTAG configuration.
1
Table 14–1
BST for configured devices
Disabling IEEE Std. 1149.1 BST circuitry
Guidelines for IEEE Std. 1149.1 boundary-scan testing
Boundary-scan description language (BSDL) support
For recommendations on how to connect a JTAG chain with
multiple voltages across the devices in the chain, refer to
Voltage Support in JTAG Chain”
Serial input pin for instructions as well as test and programming data.
A signal applied to TDI is expected to change state at the falling edge
of TCK. Data is shifted in on the rising edge of
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of
if data is not being shifted out of the device.
Input pin that provides the control signal to determine the transitions of
the Test Access Port (TAP) controller state machine. Transitions within
the state machine occur at the rising edge of
must be set up before the rising edge of
rising edge of
to be driven high.
The clock input to the BST circuitry. Some operations occur at the
rising edge, while others occur at the falling edge.
summarizes the functions of each of these pins.
TCK
. During non-JTAG operation,
CCIO
supply. All user I/O pins are tri-stated
Function
on Pg. 19.
Altera Corporation-Preliminary
TCK
.
TCK
TMS
TCK
TCK
TMS
. The pin is tri-stated
. Therefore,
is evaluated on the
.
is recommended
March 2007
TMS
“I/O