EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 365

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Automated
Single Event
Upset Detection
Altera Corporation-Preliminary
March 2007
CHANGE_EDREG
Table 13–1. CHANGE_EDREG JTAG Instruction
JTAG Instruction
Instruction Code
00 0001 0101
results in a 0 on the output signal CRC_ERROR. If a soft error occurs
within the device, the resulting signature value is non-zero and the
CRC_ERROR output signal is 1.
You can inject a soft error by changing the 32-bit CRC storage register in
the CRC circuitry. After verifying the failure induced, you can restore the
32-bit CRC value to the correct CRC value using the same instruction and
inserting the correct value. Be sure to read out the correct value first
before updating it with a known bad value.
Cyclone III devices, when in user mode, support the CHANGE_EDREG
Joint Test Action Group (JTAG) instruction, which allows you to write to
the 32-bit storage register. You can use Jam files (.jam) to automate the
testing and verification process. This is a powerful design feature that
enables you to dynamically verify the CRC functionality in-system
without having to reconfigure the device. You can then switch to use the
CRC circuit to check for real errors induced by an SEU. You can only
execute the CHANGE_EDREG JTAG instruction when the device is in user
mode.
1
Cyclone III devices offer on-chip circuitry for automated checking of SEU
detection. Applications that require the device to operate error-free at
high elevations or in close proximity to earth's North or South Pole
require periodic checks to ensure continued data integrity. The error
detection cyclic redundancy code feature controlled by the Device & Pin
Options dialog box in the Quartus II software uses a 32-bit CRC circuit to
ensure data reliability and is one of the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Cyclone III devices, eliminating the need for external logic. The CRC is
computed by the device during configuration and checked against an
automatically computed CRC during normal operation. The CRC_ERROR
After the test completes, Altera recommends that you
reconfigure the device.
This instruction connects the 32-bit CRC storage register between
TDI
register to test the operation of the error detection CRC circuitry at the
CRC_ERROR
and
TDO
. Any precomputed CRC is loaded into the CRC storage
pin.
Automated Single Event Upset Detection
Cyclone III Device Handbook, Volume 1
Description
13–3