EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 217

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III
Memory Support
Overview
Altera Corporation-Preliminary
March 2007
DDR2
SDRAM
(2)
Table 9–3. Cyclone III Maximum Clock Rate Support for External Memory Interfaces
Standard
Memory
Standard
SSTL-18
SSTL-18
class II
class I
I/O
Top/Bottom
I/O Banks
-6 Speed Grade (MHz)
Figure 9–1. Cyclone III External Memory Interface Overview
This chapter includes a description of the hardware interfaces for external
memory interfaces available in the Cyclone III devices. For more
information on implementing complete external memory interfaces, refer
to the following documents found at the Altera web site at
www.altera.com:
■
■
■
■
This section describes the interface between Cyclone III devices and
external memory standards.
rate that Cyclone III devices can support with external memory
interfaces.
200
133
ALTMEMPHY Megafunction User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide
AN 445: Interfacing DDR and DDR2 SDRAM with Cyclone III Devices
AN 438: Constraining and Analyzing Timing for External Memory
Interfaces
Altera, Third Party
or Custom Memory Controller
Cyclone III FPGA
Controller
Controller
Left/Right
I/O Banks
Memory
Memory
167
125
IP
IP
Top/Bottom
I/O Banks
-7 Speed Grade (MHz)
167
125
Commercial
/ /
Table 9–3
/ /
ALTMEMPHY
Cyclone III Device Handbook, Volume 1
PHY
PHY
Left/Right
I/O Banks
Cyclone III Memory Support Overview
IP
IP
summarizes the maximum clock
150
(3)
Top/Bottom
I/O Banks
-8 Speed Grade (MHz)
/ /
/ /
Note (1)
167
(3)
(Part 1 of 2)
Left/Right
I/O Banks
133
(3)
9–3