EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 221

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
f
When you use the Altera Memory Controller MegaCores, the PHY is
instantiated for you. For more information on the memory interface data
path, refer to the ALTMEMPHY Megafunction User Guide.
1
All the I/O banks in Cyclone III devices support DQ and DQS signals with
DQ-bus modes of ×8, ×9, ×16, ×18, ×32, and ×36. In ×8, ×16, and ×32
modes, one DQS pin drives up to 8, 16, or 32 DQ pins, respectively, within
the group, to support DDR2 and DDR SDRAM interfaces.
In the ×9, ×18, and ×36 modes, a pair of DQS pins (CQ and CQ#) drives up
to 9, 18, or 36 DQ pins, respectively, within the group, to support one, two,
or four parity bits and the corresponding data bits. The ×9, ×18, and ×36
modes support the QDRII memory interface. CQ# is the inverted
read-clock signal which is connected to the complementary data strobe
(DQS#) pin. You can use any unused DQ pins as regular user I/O pins if
they are not used as memory interface signals.
number of DQS/DQ groups supported on each side of the Cyclone III
device.
ALTMEMPHY is a self-calibrating megafunction, enhanced to
simplify the implementation of the read-data path in different
memory interfaces. The auto-calibration feature of
ALTMEMPHY provides ease-of-use by optimizing clock phases
and frequencies across process, voltage, and temperature (PVT)
variations. You can save on the global clock resources in Cyclone
III devices through the ALTMEMPHY megafunction because
you do not need to route the DQS signals on the global clock
buses (because DQS is ignored for read capture).
Resynchronization issues do not arise because no transfer occurs
from the memory domain clock (DQS) to the system domain for
capturing data DQ.
Cyclone III Memory Interfaces Pin Support
Cyclone III Device Handbook, Volume 1
Table 9–4
shows the
9–7