EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 430
EP3C16F256I7
Manufacturer Part Number
EP3C16F256I7
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C16F256I7.pdf
(582 pages)
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Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
f
Device operation in Mbps
t
TCCS
Output jitter (peak to peak)
t
t
t
HSCLK
DUTY
RISE
FALL
LOCK
Table 1–25. Dedicated RSDS Transmitter Timing Specification (2),
Pending silicon characterization.
Values for device speed grade -7 and -8 will be available after characterization.
Dedicated RSDS is only supported at output pin of Row I/O (Bank 1, 2, 5 and 6).
(input clock frequency)
Table
Symbol
1–25:
Periphery Performance
High-Speed I/O Specification
Table 1–25
devices. See
specifications.
to
”Glossary”
Table 1–34
20–80%
80–20%
Modes
x10
x10
x8
x7
x4
x2
x1
x8
x7
x4
x2
x1
for definitions of high-speed timing
show the high-speed I/O timing for Cyclone III
Min
100
(1)
10
10
10
10
10
10
80
70
40
20
10
(3)
-6 Speed Grade
Typ
(1)
(1)
Cyclone III Handbook
Max
180
180
180
180
180
360
360
360
360
360
360
360
(1)
(1)
(1)
(1)
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ns
ps
ps
ps
%
1–20
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