EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 293

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
1
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10 KΩ
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA[0] pin. The configuration data is clocked
into the target device until CONF_DONE goes high. The CONF_DONE pin
must have an external 10 KΩ pull-up resistor in order for the device to
initialize.
When you use a download cable, setting the Auto-restart configuration
after error option does not affect the configuration cycle because you
must manually restart configuration in the Quartus II software when an
error occurs. Additionally, the Enable user-supplied start-up clock
(CLKUSR) option has no affect on the device initialization because this
option is disabled in the SRAM Object File when programming the device
using the Quartus II programmer and download cable. Therefore, if you
turn on the CLKUSR option, you do not need to provide a clock on
CLKUSR when you are configuring the device with the Quartus II
programmer and a download cable.
for Cyclone III devices using a USB Blaster, MasterBlaster, ByteBlaster II,
or ByteBlasterMV cable.
To begin configuration, power the V
the banks where the configuration and JTAG pins reside)
voltages to the appropriate voltage levels.
Cyclone III Device Handbook, Volume 1
Figure 10–18
Passive Serial Configuration
CCINT
shows PS configuration
, V
CCA
, and V
CCIO
10–57
(for