EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 579

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Letter
Table 1–104. Glossary
U
T
t
TCCS (Channel-to-
channel-skew)
tcin
t
tcout
t
t
t
Timing Unit Interval
(TUI)
t
t
t
tpllcin
tpllcout
Transmitter Output
Waveform
t
tSU
C
CO
D U T Y
FA L L
H
I N J I T T E R
O U T J I T T E R _ D E D C L K
O U T J I T T E R _ I O
R I S E
Term
—
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest
output edges, including t
TCCS measurement.
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal High-to-low transition time (80-20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays,
and data sampling window. (TUI = 1/(Receiver Input Clock Frequency
Multiplication Factor) = t
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS
Differential I/O Standard
Signal Low-to-high transition time (20-80%).
Input register setup time.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V os
V
OD
C
CO
/w).
variation and clock skew. The clock is included in the
V
OD
Definitions
—
V
OD
Cyclone III Handbook
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p − n (1)
1–169
OH
OL