EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 44

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EP3C16F256I7

Manufacturer Part Number
EP3C16F256I7
Description
Cyclone III
Manufacturer
Altera
Datasheet

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MultiTrack Interconnect in Cyclone III Devices
3–2
Cyclone III Device Handbook, Volume 1
Row Interconnects
Row interconnects route signals to and from logic array blocks (LABs),
phase-locked loops (PLLs), M9K memory blocks, and embedded
multipliers within the same row. These row resources include:
The direct link interconnect allows blocks to drive into the local
interconnect of its left and right neighbors. The direct link interconnect
provides fast communication between adjacent blocks without using row
interconnect resources.
The R4 interconnects span four LABs, three LABs, and one M9K memory
block, or three LABs and one embedded multiplier to the right or left of a
source LAB. These resources are used for fast row connections in a
four-LAB region. Every LAB has its own set of R4 interconnects to drive
either left or right.
LAB. The R4 interconnects can drive and be driven by LABs, M9K
memory blocks, embedded multipliers, PLLs, and row input/output
elements (IOEs). For LAB interfacing, a primary LAB or LAB neighbor
(see
that drive to the right, the primary LAB and right neighbor can drive on
to the interconnect. For R4 interconnects that drive to the left, the primary
LAB and its left neighbor can drive on to the interconnect. R4
interconnects can drive other R4 interconnects to extend the range of
LABs they can drive. Additionally, R4 interconnects can drive R24
interconnects, C4, and C16 interconnects for connections from one row to
another.
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 interconnects for high-speed access across the length of the
device
Figure
3–1) can drive a given R4 interconnect. For R4 interconnects
Figure 3–1
shows R4 interconnect connections from a
Altera Corporation-Preliminary
March 2007

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