EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 378

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
IEEE Std. 1149.1
Boundary-Scan
Register
14–4
Cyclone III Device Handbook, Volume 1
f
IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port
(TAP) controller. For more information on the TAP controller, refer to the
“IEEE Std. 1149.1 BST Operation Control”
operate the TAP controller, and the TDI and TDO pins provide the serial
path for the data registers. The TDI pin also provides data to the
instruction register, which then generates control logic for the data
registers.
The boundary-scan register is a large serial shift register that uses the TDI
pin as an input and the TDO pin as an output. The boundary-scan register
consists of 3-bit peripheral elements that are associated with Cyclone III
I/O pins. You can use the boundary-scan register to test external pin
connections or to capture internal data.
For more information on the Cyclone III device family’s boundary-scan
register lengths, refer to the Configuring Cyclone III Devices chapter of the
Cyclone III Device Handbook.
Figure 14–3
of the IEEE Std. 1149.1 device.
Figure 14–3. Boundary-Scan Register
TDI
shows how test data is serially shifted around the periphery
TMS
TAP Controller
Internal Logic
TCK
section. The TMS and TCK pins
Altera Corporation-Preliminary
TDO
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
March 2007