MCP4706A3T-E/CH Microchip Technology, MCP4706A3T-E/CH Datasheet - Page 45

• Manufacturer Part Number: MCP4706A3T-E/CH
• Description: Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP4706A3T-E/CH

• Number Of Converters: 1
• Conversion Rate: 1
• Resolution: 8 bit
• Interface Type: I2C
• Settling Time: 6 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Maximum Power Dissipation: 452 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 210 uA
• Number Of Bits: 8
• Data Interface: EEPROM, I²C, Serial
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 452mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs And Type: *
• Lead Free Status / Rohs Status: Details

5.3.1.4
The Repeated Start bit (see
current
communicating with the current Slave Device without
releasing the I
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5:
Waveform.
FIGURE 5-7:
FIGURE 5-8:
© 2011 Microchip Technology Inc.
SDA
SCL
SDA
SCL
Note 1: A bus collision during the Repeated Start
SDA
SCL
Master
• SCL goes low before SDA is asserted
• SDA is sampled low when SCL goes
S
condition occurs if:
Repeated Start Bit
low. This may indicate that another
master is attempting to transmit a
data "1".
from low to high.
2
C bus. The Repeated Start condition is
Device
1st Bit
Condition
Repeat Start Condition
Typical 8-Bit I
I
START
2
C Data States and Bit Sequence.
Figure
wishes
2nd Bit 3rd Bit
Sr = Repeated Start
5-5) indicates the
Data allowed
to change
2
C Waveform Format.
to
1st Bit
continue
4th Bit
Data or
A valid
5th Bit
5.3.1.5
The Stop bit (see
I
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I
devices.
FIGURE 5-6:
Transmit Mode.
5.3.2
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP47X6 will not stretch the clock signal (SCL)
since memory read access occurs fast enough.
5.3.3
If any part of the I
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
2
SDA A / A
SCL
C Data Transfer Sequence. The Stop bit is defined as
MCP4706/4716/4726
6th Bit
CLOCK STRETCHING
ABORTING A TRANSMISSION
7th Bit
Stop Bit
Figure
2
C transmission does not meet the
8th Bit
Stop Condition Receive or
Condition
2
STOP
C interface of all MCP47X6
5-6) Indicates the end of the
A / A
DS22272A-page 45
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