MCP4706A3T-E/CH Microchip Technology, MCP4706A3T-E/CH Datasheet - Page 52

• Manufacturer Part Number: MCP4706A3T-E/CH
• Description: Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP4706A3T-E/CH

• Number Of Converters: 1
• Conversion Rate: 1
• Resolution: 8 bit
• Interface Type: I2C
• Settling Time: 6 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Maximum Power Dissipation: 452 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 210 uA
• Number Of Bits: 8
• Data Interface: EEPROM, I²C, Serial
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 452mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs And Type: *
• Lead Free Status / Rohs Status: Details

MCP4706/4716/4726
6.3
This write command is used to update the volatile and
nonvolatile (EEPROM) DAC Register value and
configuration bits.
write command.
• V
• EEPROM update: At the falling edge of the
The DAC register and Power-down configuration bits
(volatile and EEPROM) are updated with the written
date at the completion of the ACK bit (falling edge of
SCL). The EEPROM memory requires time (T
the values to be written. Another Write All memory
command should not be issued until the EEPROM
write is complete.
FIGURE 6-3:
DS22272A-page 52
Acknowledge pulse of the 4th byte.
Acknowledge pulse of the 4th byte.
Note 1:
SDA
SCL
Legend:
OUT
2:
3:
update: At the falling edge of the
Write All Memory
(C2:C0 = ‘011’)
S
Start bit
The 2nd - 4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit.
ACK bit generated by MCP47X6.
The device updates V
1
D09:D00 = 10-bit data for MCP4716 device
D07:D00 = 8-bit data for MCP4706 device
D11:D00 = 12-bit data for MCP4726 device
X = don’t care
MCP4726
MCP4716
MCP4706
Device Addressing
1
Figure 6-3
0
Write All Memory Command.
0
D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
D07 D06 D05 D04 D03 D02 D01 D00
b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00
A2 A1 A0
shows an example of this
OUT
at the falling edge of the SCL at the end of this ACK pulse.
R/W
0
Read/Write bit (Write)
A
ACK bit
0
Command
bits
0
WC
Data bits (16 bits) (3rd + 4th bytes)
(3)
1
) for
1
VREF1
Ref.
Voltage
Select
bits
VREF0
PD1 PD0
Power
Down
bits
Write commands which only update volatile memory
(C2:C0 = ‘00x’ or ‘010’) can be issued. Read
commands and the General Call commands may not
be issued.
Note:
X
Gain
bit
X
G
ACK bit
A
RDY/BSY bit toggles to “low” and back to
“high”
completed. The state of the RDY/BSY bit
can be monitored by a read command.
0
X
X
b15 b14 b13 b12 b11 b10 b09 b08
b07 b06 b05 b04 b03 b02 b01 b00
X
X
Data bits (8 bits) (3rd byte)
Data bits (8 bits) (4th byte)
(3)
after
X
X
X
© 2011 Microchip Technology Inc.
X
X
X
the
X
X
X
EEPROM write
ACK bit
ACK bit
X
X
X
(3)
(3)
Note 1
Note 2
A
A
Stop bit
0
0
P
is