MCP4706A3T-E/CH Microchip Technology, MCP4706A3T-E/CH Datasheet - Page 71

• Manufacturer Part Number: MCP4706A3T-E/CH
• Description: Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP4706A3T-E/CH

• Number Of Converters: 1
• Conversion Rate: 1
• Resolution: 8 bit
• Interface Type: I2C
• Settling Time: 6 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Maximum Power Dissipation: 452 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 210 uA
• Number Of Bits: 8
• Data Interface: EEPROM, I²C, Serial
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 452mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs And Type: *
• Lead Free Status / Rohs Status: Details

8.10
In the design of a system with the MCP4706/4716/4726
devices, the following considerations should be taken
into account:
•
•
8.10.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (V
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
FIGURE 8-10:
Connections.
© 2011 Microchip Technology Inc.
SS
Power Supply Considerations
Layout Considerations
V
V
OUT
REF
should reside on the analog plane.
Design Considerations
POWER SUPPLY
CONSIDERATIONS
0.1 µF
V
V
Typical Microcontroller
DD
SS
Figure 8-10
0.1 µF
SDA
SCL
illustrates an
V
V
DD
SS
DD
DD
) as
and
8.10.2
Several layout considerations may be applicable to
your application. These may include:
•
•
8.10.2.1
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP47X6’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is
environments may require shielding of critical signals.
Separate digital and analog ground planes are
recommended. In this case, the V
pins of the V
analog ground plane.
8.10.2.2
In some applications, PCB area is a criteria for device
selection.
dimensions and area for the different package options.
The table also shows the relative area factor compared
to the smallest area. For space critical applications, the
DFN package would be the suggested package.
TABLE 8-2:
6
6
MCP4706/4716/4726
Noise
PCB Area Requirements
Note:
Note 1: Does not include recommended land
capable
SOT-23
DFN
Package
Type
Table 8-2
LAYOUT CONSIDERATIONS
Breadboards and wire-wrapped boards
are not recommended.
DD
pattern dimensions. Dimensions are
typical values.
Noise
PCB Area Requirements
Code
capacitors should be terminated to the
of
CH
MA
PACKAGE FOOTPRINT
providing.
Length Width
shows the typical package
Dimensions
2.90
2.00
(mm)
Package Footprint
SS
2.70
2.00
Particularly
pin and the ground
DS22272A-page 71
7.83
4.00
(
1
1.96
harsh
)
1