MCP4706A3T-E/CH Microchip Technology, MCP4706A3T-E/CH Datasheet - Page 50

• Manufacturer Part Number: MCP4706A3T-E/CH
• Description: Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 SOT-23 T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP4706A3T-E/CH

• Number Of Converters: 1
• Conversion Rate: 1
• Resolution: 8 bit
• Interface Type: I2C
• Settling Time: 6 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Maximum Power Dissipation: 452 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 210 uA
• Number Of Bits: 8
• Data Interface: EEPROM, I²C, Serial
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 452mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs And Type: *
• Lead Free Status / Rohs Status: Details

MCP4706/4716/4726
6.1
This command is used to update the volatile DAC
Register value and the two Power-down configuration
bits (PD1:PD0). This command is typically used for a
quick update of the analog output by modifying the
minimum parameters. The EEPROM values are not
affected by this command.
Figure 6-1
where a stop bit completes the command.
The
configuration bits are updated with the written date at
the completion of the ACK bit (falling edge of SCL).
FIGURE 6-1:
DS22272A-page 50
Note 1:
SDA
SCL
Legend:
volatile
2:
3:
Write Volatile DAC Register
(C2:C0 = ‘00x’)
S
Start bit
The 2nd - 3rd bytes can be repeated after the 3rd byte by continued clocking before issuing Stop bit.
ACK bit generated by MCP47X6.
The device updates V
shows an example of the command format,
1
D09:D00 = 10-bit data for MCP4716 device
D07:D00 = 8-bit data for MCP4706 device
D11:D00 = 12-bit data for MCP4726 device
X = don’t care
Device Addressing
1
DAC
0
Write Volatile DAC Register Command.
0
register
A2 A1 A0
OUT
MCP4726
MCP4716
MCP4706
at the falling edge of the SCL at the end of this ACK pulse.
and
R/W
0
Read/Write bit (Write)
A
Command
bits
Power-down
ACK bit
0
b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00
D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
X
0
(3)
0
X
Power
Down
bits
PD1 PD0 b11 b10 b09 b08
X
Data bits (4 bits)
X
After this ACK bit, the I
Stop bit or the I
command bits + 2 power down bits + 4 data bits
(b11:b08)) and the 3rd byte (8 data bits (b07:b00)).
Repeating the 2nd and 3rd bytes allows a continuous
command where the volatile DAC register can be
updated without the communication overhead of the
device addressing byte (1st byte).
The device updates the V
Acknowledge pulse of the 3rd byte.
D07 D06 D05 D04 D03 D02 D01 D00
Data bits (12 bits)
ACK bit
A
0
b07 b06 b05 b04 b03 b02 b01 b00
2
(3)
C Master can repeat the 2nd (2
Data bits (8 bits)
© 2011 Microchip Technology Inc.
2
C Master should generate a
OUT
at the falling edge of the
X
ACK bit
X
(3)
Note 1
Note 2
A
Stop bit
0
P