NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 173

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.14.12.1
5.14.13
5.14.13.1
5.14.13.2
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Clock Control Signals from Intel
Synthesizer (Mobile Only)
The clock generator is assumed to have direct connect from the following ICH6 signals:
Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various hardware
mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle,
detecting when the whole system is idle, and detecting when accesses are attempted to idle
subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM calls, there is
no quick way to know when the system is idle between keystrokes. The ICH6 does not support
burst modes.
APM Power Management (Desktop Only)
The ICH6 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable
register, generates an SMI# once per minute. The SMI handler can check for system activity by
reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can
increment a software counter. When the counter reaches a sufficient number of consecutive
minutes with no activity, the SMI handler can then put the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by
writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices
(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.
Other PCI activity can be monitored by checking the PCI interrupts.
Mobile APM Power Management (Mobile Only)
In mobile systems, there are additional requirements associated with device power management.
To handle this, the ICH6 has specific SMI# traps available. The following algorithm is used:
The SMI# handler exits with an I/O restart. This allows the original software to continue.
1. The periodic SMI# timer checks if a device is idle for the require time. If so, it puts the device
2. When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle
3. The SMI# handler turns on the device and turns off the trap
•
•
•
STP_CPU#
STP_PCI#
SLP_S3#
into a low-power state and sets the associated SMI# trap.
does not really go to the device and an SMI# is generated).
due to CLKRUN# protocol
Expected to drive clock chip PWRDOWN (through inverter), to stop
clocks in S3
Stops processor clocks in C3 and C4 states
Stops system PCI clocks (not the ICH6 free-running 33 MHz clock)
HOT
®
and on the way to S3
ICH6 to Clock
COLD
Functional Description
to S5.
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