NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 399

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.8.1.5
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
This register is used to enable C-state related modes.
Bit
7:4
3:2
1:0
Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the ICH6 waits for from
the de-assertion of DPRSLPVR to the de-assertion of STP_CPU#. This provides a programmable
time for the processor’s voltage to stabilize when exiting from a C4 state. This thus changes the
value for t266.
DPSLP-TO-SLP — R/W. This field selects the DPSLP# de-assertion to CPU_SLP# de-assertion
time (t270). Normally this value is determined by the CPU_PLL_LOCK_TIME field in the
GEN_PMCON_2 register. When this field is non-zero, then the values in this register have higher
priority. It is software’s responsibility to program these fields in a consistent manner.
Bits
00b
01b
10b
11b
Bits
00b
01b
10b
11b
AAh
00h
No
Core
Use value is
CPU_PLL_LOCK_TIME
field (default is 30 µs)
20 µs
15 µs
10 µs
t266
95 µs
22 µs
min
t270
t266
101 µs
28 µs
max
Default
Value used for “Fast”
VRMs
Reserved
Reserved
Comment
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
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