NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 199
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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5.19.8
Intel
Figure 5-9. USB Legacy Keyboard Flow Diagram
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may
not boot, and MS-DOS legacy software will not run, because the keyboard will not be identified.
The ICH6 implements a series of trapping operations which will snoop accesses that go to the
keyboard controller, and put the expected data from the USB keyboard into the keyboard
controller.
LPC bus.
This legacy operation is performed through SMM space.
path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because
the enable is after the latch, it is possible to check for other events that didn't necessarily cause an
SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes
active) to ensure that the processor doesn't complete the cycle before the SMI is observed. This
method is used on MPIIX and has been validated.
The logic also needs to block the accesses to the 8042. If there is an external 8042, then this is
simply accomplished by not activating the 8042 CS. This is simply done by logically ANDing the
four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go
active. An additional term is required for the “pass-through” case.
The state table for
KBC Accesses
PCI Config
Read, Write
USB_IRQ
Clear USB_IRQ
Figure 5-9
Decoder
Comb.
EN_SMI_ON_IRQ
EN_PIRQD#
Clear SMI_60_R
60 READ
is shown in
S
R
D
EN_SMI_ON_60R
Table
Same for 60W, 64R, 64W
5-44.
S
R
AND
AND
D
Figure 5-9
AND
shows the Enable and Status
Functional Description
To "Caused By" Bit
To PIRQD#
To Individual
"Caused By"
"Bits"
OR
SMI
199
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