NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 703

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

19.1.44
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
29:21
20:18
17:15
14:8
Bit
6:2
31
30
7
1
0
Power Management SCI Enable (PMCE) — R/W.
0 = SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is detected.
Hot Plug SCI Enable (HPCE) — R/W.
0 = SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Reserved
Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit Latency for unique-
clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3:Offset 50h:bit 6). It defaults to 512 ns to less
than 1 µs, but may be overridden by BIOS.
Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit Latency for
common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3:Offset 50h:bit 6). It defaults to 128
ns to less than 256 ns, but may be overridden by BIOS.
Reserved
Port I/OxApic Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
Reserved
Hot Plug SMI Enable (HPME) — R/W.
0 = SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
Power Management SMI Enable (PMME) — R/W.
0 = SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is detected.
Port #
1
2
3
4
D8
00110000h
FEC1_0000h – FEC1_7FFFh
FEC1_8000h – FEC1_FFFFh
FEC2_0000h – FEC2_7FFFh
FEC2_8000h – FEC2_FFFFh
–
DBh
Address
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/W
32 bits
703