NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 699

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

19.1.35
19.1.36
19.1.37
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
MID—Message Signaled Interrupt Identifiers Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
MC—Message Signaled Interrupt Message Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
MA—Message Signaled Interrupt Message Address
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
15:8
15:8
31:2
Bit
7:0
Bit
6:4
3:1
Bit
1:0
7
0
Next Pointer (NEXT) — RO. This field indicates the location of the next pointer in the list.
Capability ID (CID) — RO. Capabilities ID indicates MSI.
Reserved
64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME) — R/W. These bits are R/W for software compatibility, but only
one message is ever sent by the root port.
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W.
0 = MSI is disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
NOTE: CMD.BME (D28:F0/F1/F2/F3:04h:bit 2) must be set for an MSI to be generated. If
Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DW
aligned.
Reserved
CMD.BME is cleared, and this bit is set, no interrupts (not even pin based) are generated.
80–81h
9005h
82–83h
0000h
84
00000000h
–
87h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
RO
16 bits
R/W, RO
16 bits
R/W
32 bits
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