NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 480

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.1.41
.
12.1.42
.
12.1.43
480
ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset:
Default Value:
SP—Scratch Pad Register (SATA–D31:F2)
Address Offset:
Default Value:
BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset:
Default Value:
(Desktop
(Mobile
31:0
31:14
Only)
Only)
Bit
7:4
Bit
Bits
3
2
1
0
13
13
12
Reserved
Secondary Slave Trap (SST) — R/WC. This bit indicates that a trap occurred to the secondary
slave device.
Secondary Master Trap (SPT) — R/WC. This bit indicates that a trap occurred to the secondary
master device.
Primary Slave Trap (PST) — R/WC. This bit indicates that a trap occurred to the primary slave
device.
Primary Master Trap (PMT) — R/WC. This bit indicates that a trap occurred to the primary master
device.
Data (DT) — R/W. This is a read/write register that is available for software to use. No hardware
action is taken on this register.
Reserved
Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 3, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 3 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
Reserved.
Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
C4h
00h
D0h
00000000h
E0h
00000000h
–
E3h
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/WC
R/W
32 bits
32 bits
8 bits
R/W, R/WC