NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 296

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LAN Controller Registers (B1:D8:F0)
8.2.2
296
SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
The processor places commands for the Command and Receive units in this register. Interrupts are
also acknowledged in this register.
Bit
15
14
13
12
10
11
9
8
CX Mask (CX_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CX interrupt.
FR Mask (FR_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FR interrupt.
CNA Mask (CNA_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CNA interrupt.
RNR Mask (RNR_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an RNR interrupt.
ER Mask (ER_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an ER interrupt.
FCP Mask (FCP_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FCP interrupt.
Software Generated Interrupt (SI) — WO.
0 = No Effect.
1 = Setting this bit causes the LAN controller to generate an interrupt.
Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s assertion of the INTA#
signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit.
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
02
0000h
–
03h
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
16 bits
R/W, WO