NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 276

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.55
276
BUC—Backed Up Control Register
Offset Address:
Default Value:
All bits in this register are in the RTC well and only cleared by RTCRST#
(Desktop)
(Mobile)
Bit
7:3
2
1
1
0
Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by RSMRST#, but not
PLTRST# nor CF9h writes.
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and INIT3_3V# will
PATA Reset State (PRS) — R/W.
0 = The reset state of the PATA pins will be driven.
1 = The reset state of the PATA pins will be tri-state.
Reserved
Top Swap (TS) — R/W.
0 = Intel
1 = ICH6 will invert A16 for cycles going to the BIOS space (but not the feature space) in the
If ICH is strapped for Top-Swap (GNT[6]# is low at rising edge of PWROK), then this bit cannot be
cleared by software. The strap jumper should be removed and the system rebooted.
go inactive with the same timings as the other processor I/F signals (hold time after
CPURST# inactive).
FWH.
3414–3414h
0000001xb (Mobile)
0000000xb (Desktop)
®
ICH6 will not invert A16.
Intel
®
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W
8-bit