NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 544

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.2
14.2.1
14.2.1.1
544
Table 14-2. Enhanced Host Controller Capability Registers
Note: The ICH6 EHCI controller will not accept memory transactions (neither reads nor writes) as a
Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory range are
Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers: Capability Registers
and Operational Registers.
target that are locked transactions. The locked transactions should not be forwarded to PCI as the
address space is known to be allocated to USB.
ignored and result a master abort. Similarly, if the Memory Space Enable (MSE) bit (D29:F7:04h,
bit 1) is not set in the Command register in configuration space, the memory range will not be
decoded by the ICH6 enhanced host controller (EHC). If the MSE bit is not set, then the ICH6 must
default to allowing any memory accesses for the range specified in the BAR to go to PCI. This is
because the range may not be valid and, therefore, the cycle must be made available to any other
targets that may be currently using that range.
Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural parameters
register is writable. These registers are implemented in the suspend well and is only reset by the
standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset.
NOTE: “Read/Write Special” means that the register is normally read-only, but may be written when the
CAPLENGTH—Capability Registers Length Register
Offset:
Default Value:
MEM_BASE
+ Offset
Bit
7:0
08–0Bh
02–03h
04–07h
00h
WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during
initialization, their contents must not get modified by HCRESET or D3-to-D0 internal reset.
Capability Register Length Value — RO. This register is used as an offset to add to the Memory
Base Register (D29:F7:10h) to find the beginning of the Operational Register Space. This field is
hardwired to 20h indicating that the Operation Registers begin at offset 20h.
HCCPARAMS
HCIVERSION
HCSPARAMS
CAPLENGTH
Mnemonic
MEM_BASE + 00h
20h
Capabilities Registers Length
Host Controller Interface Version Number
Host Controller Structural Parameters
Host Controller Capability Parameters
Intel
Register
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
RO
8 bits
00104208h
00006871h
Default
0100h
20h
(special), RO
Type
R/W
RO
RO
RO