NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 197

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it is said to
be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active
bit in the TD being cleared to 0 and the Stalled and Babble bits being set to 1. The C_ERR field is
not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the
end of the frame. A hardware interrupt is signaled to the system.
If an EOF babble was caused by the ICH6 (due to incorrect schedule for instance), the ICH6 forces
a bit stuff error followed by an EOP and the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a transaction or
that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is
cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is
signaled to the system.
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred
for this transaction. This would generally be caused by the ICH6 not being able to access required
data buffers in memory within necessary latency requirements. Either of these conditions causes
the C_ERR field of the TD to be decremented.
When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set, the USB
Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware
interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that six 1s in a row within the
incoming data stream. This causes the C_ERR field of the TD to be decremented. When the
C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the
USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware
interrupt is signaled to the system.
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Intel
I/O Controller Hub 6 (ICH6) Family Datasheet
197