PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 109

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
6.7
Refer to
biter terminology used here. The VI unit uses internal
buffering before writing data to SDRAM. There are two
internal buffers, each 16 entries of 32 bits.
In fullres mode, each internal buffer is used for 128 Y
samples, 64 U samples, and 64 V samples. Once the first
internal buffer is filled, 4 highway transactions must oc-
cur before the second buffer fills completely. Hence, the
requirement for not losing samples is:
• 4 requests must be served within 256 VI clock
For the typical CCIR601-resolution NTSC or PAL 27-
MHz VI clock rate, the latency requirement is 4 requests
in 9481 ns (25600/27). This can be used as one request
every 2370 ns or, with a PNX1300 SDRAM clock speed
of 100 MHz, every 237 SDRAM clock cycles. The one re-
quest latency is used to define the priority raising value
(see
In halfres mode, the Y, U, and V decimation by 2 takes
place before writing to the internal buffers. So, the re-
quirement for not loosing samples is:
• 4 requests served within 512 VI clock cycles.
For halfres subsampling, NTSC or PAL 27-MHz VI clock
rate and PNX1300 SDRAM clock speed of 100 MHz, la-
tency is 4 requests in 51200/27 = 18962 ns (1896 high-
way clock cycles) or one request every 4740 ns (474
SDRAM clock cycles).
For raw8 capture and message passing modes, each in-
ternal buffer stores 64 samples at the incoming VI clock
rate. The latency requirement is one request served ev-
ery 64 VI clock cycles.
For the raw10 capture modes, each internal buffer stores
32 samples. Hence, the requirement for not losing sam-
ples is one request served every 32 VI clock cycles.
cycles.
Section 20.6.3 on page
HIGHWAY LATENCY AND HBE
Chapter 20, “Arbiter,”
20-8).
for a description of the ar-
For a 38-MHz data rate on the incoming 10-bit samples
and a PNX1300 SDRAM clock speed of 100 MHz, high-
way latency should be set to guarantee less than 3200/
38 = 842 ns (84 SDRAM clock cycles) per clock cycle.
This cannot be met if any other peripherals are enabled.
Table 6-4
tency (in SDRAM clock cycles) needed to guarantee that
no samples are lost. The general formula uses ‘F’ to rep-
resent the VI clock frequency (in MHz).
Table 6-4. VI highway latency requirements (27-MHz
data rate, 100-MHz PNX1300 highway clock)
In fullres mode, bandwidth requirements (in bytes) per
video line with active image for VI is:
• B
ceil(X) function is the least integral value greater than or
equal to X.
In halfres mode, the bandwidth is:
• B
Raw8 mode and message passing mode bandwidth de-
pends only on VI clock speed. For raw10 mode each 10-
bit value counts as 2 bytes for bandwidth computations.
PRELIMINARY SPECIFICATION
fullres capture
halfres capture
raw8
raw10s
raw10u
message passing
fullr
halfr
Mode
= ceil(WIDTH*2/256) * 4 * 64
= ceil(WIDTH*2/512) * 4 * 64
summarizes the maximum allowed highway la-
Max latency setting
(27 MHz, 100 MHz)
237
474
237
237
118
118
Formula
12,800/F
6,400/F
6,400/F
3,200/F
3,200/F
6,400/F
Video In
6-13