PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 147

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
9.4
Figure 9-1
AO unit. At the heart of the clock system is a square
wave DDS (Direct Digital Synthesizer). The DDS can be
programmed to emit frequencies from approx. 1 Hz to 80
MHz with a sub Hertz resolution.
The output of the DDS is always sent to the AO_OSCLK
output pin. This output is intended to be used as the
256f
converters, such as the Philips SAA7322, or codecs
such as the AD1847, CS4218, or UAD1340.
The PNX1300 DDS frequency is set by writing to the
FREQUENCY MMIO register. The programmer is free to
change the FREQUENCY setting dynamically, in order
to adjust the outgoing audio sample rate. In ATSC trans-
port stream decoding, this is the method by which the
system software locks audio output sample rate to the
original program provider sample rate.
Depending on bit 31 (MSB), the DDS runs in one of the
two following modes:
• bit 31 = 1 (standard improved mode)
• bit 31 = 0 (TM-1000 compatibility mode)
9.4.1
This mode was first available in the TM-1100. In this
mode, a high quality, low-jitter AO_OSCLK is generated.
The setting of the FREQUENCY register to accomplish a
given AO_OSCLK frequency is given by the formula:
Figure 9-1. AO clock system and I/O interface
s
AO_OSCLK
or 384f
AO_SCK
INTERNAL CLOCK SOURCE
AO_SDx
AO_WS
PNX1300 Standard Improved Mode
illustrates the different clock capabilities of the
s
(e.g. 256×f
(e.g. 64×f
system clock source for oversampling D/A
s
s
)
)
Parallel to Serial Converter
div N+1
div N+1
SER_MASTER
8
7
16
16
32
WSDIV
SCKDIV
RIGHT[15:0]
LEFT[15:0]
AO_CC[31:0]
This mode, and the above formula, should be used for all
new software development on PNX1300.
Table 9-2. Clock system setting (f
In the improved mode the DDS synthesizer maximum jit-
ter can be computed as follows:
Example of jitter values can be found in
Table 9-3. Jitter values for common DSPCPU MHz
PRELIMINARY SPECIFICATION
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
9 × DSPCPUCLK
f
DSPCPU
(MHz)
FREQUENCY
jitter
f
143
166
s
0
0
=
OSCLK
256fs
256fs
384fs
384fs
---------------------------- -
9 f
31
⋅
(nSec)
0.777
0.669
jitter
DSPCPU
1
=
SCK
64fs
64fs
64fs
64fs
2
31
Square Wave DDS
FREQUENCY
+
f
f
----------------------------- -
DSPCPU
9 f
(MHz)
OSCLK
FREQUENCY
180
200
2187991971
2191574340
2208246133
2213619686
⋅
DSPCPU
DSPCPU
⋅
2
Table
32
=133 MHz)
Audio Out
(nSec)
0.617
0.555
jitter
9-3.
SCKDIV
3
3
5
5
0
9-3