PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 30

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
1-4
MM_DQM0
MM_DQM1
MM_DQM2
MM_DQM3
PCI_CLK
PCI_AD00
PCI_AD01
PCI_AD02
PCI_AD03
PCI_AD04
PCI_AD05
PCI_AD06
PCI_AD07
PCI_AD08
PCI_AD09
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_IDSEL
PCI_DEVSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
Pin Name
PCI Interface (Note: current buffer design allows drive/receive from either 3.3 or 5V PCI bus)
BGA
Ball
R18
T19
M2
M1
M3
R3
R2
R1
N2
N1
D1
D3
C1
C2
C3
C4
C6
D2
H1
G2
G1
H2
V1
V4
T2
T1
P2
P1
L2
L1
K1
K2
B2
B1
A1
A3
B4
A4
A5
B6
A6
B3
E2
E1
F3
A2
F1
B7
B5
J1
J2
J3
PRELIMINARY SPECIFICATION
NORM3
Type
Pad
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Mode
OUT
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
MM_DQ Mask Enable; these are byte enable signals for the 32-bit MM_DQ bus
All PCI input signals are sampled with respect to the rising edge of this clock. All PCI
outputs are generated based on this clock. Clock is required for normal operation of
the PCI block.
Multiplexed address and data.
Multiplexed bus commands and byte enables. High for command, low for byte enable.
Even parity across AD and C/BE lines.
Sustained tri-state. Frame is driven by a master to indicate the beginning and duration
of an access.
Sustained tri-state. Initiator Ready indicates that the bus master is ready to complete
the current data phase.
Sustained tri-state. Target Ready indicates that the bus target is ready to complete the
current data phase.
Sustained tri-state. Indicates that the target is requesting that the master stop the cur-
rent transaction.
Used as chip select during configuration read/write cycles.
Sustained tri-state. Indicates whether any device on the bus has been selected.
Driven by PNX1300/01/02/11 as PCI bus master to request use of the PCI bus.
Indicates to PNX1300/01/02/11 that access to the bus has been granted.
Sustained tri-state. Parity error generated/received by PNX1300/01/02/11.
System error. This signal is asserted when operating as target and detecting an
address parity error.
Description
Philips Semiconductors