PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 231

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 14-8. Line start and pixel time for linear model,
no other load on SDRAM
Table 14-9. Line start and pixel time for linear model,
SDRAM loaded 95%, priority delay = 1
horizontal filter, 1 component
horizontal filter, 3 components YUV
4:2:2
vertical filter, 1 component
vertical filter, 3 components YUV 4:2:2
yuv to rgb8a, pci output
yuv to rgb15a, pci output
yuv to rgb24, pci output
yuv to rgb24a, pci output
yuv to rgb8a, sdram output
yuv to rgb15a, sdram output
yuv to rgb24, sdram output
yuv to rgb24a, sdram output
yuv to rgb8a, bitmask, pci output
yuv to rgb8a, rgbl15a overlay, pci output
yuv to rgb8a, rgbl24a overlay, pci output
yuv to rgb8a, yuv422a overlay, pci out-
put
yuv to rgb8a, 422sequencing, pci output
horizontal filter, 1 component
horizontal filter,3 components YUV 4:2:2
vertical filter, 1 component
vertical filter, 3 components YUV 4:2:2
yuv to rgb8a, pci output
yuv to rgb15a, pci output
yuv to rgb24, pci output
yuv to rgb24a, pci output
yuv to rgb8a, sdram output
yuv to rgb15a, sdram output
yuv to rgb24, sdram output
yuv to rgb24a, sdram output
yuv to rgb8a, bitmask, pci output
yuv to rgb8a, rgbl15a overlay, pci output
yuv to rgb8a, rgbl24a overlay, pci output
yuv to rgb8a, yuv422a overlay, pci output
yuv to rgb8a, 422sequencing, pci output
function
function
t/linestart
t/linestart
(µs)
1.1
3.3
5.3
(µs)
3.2
0.2
0.7
3.2
3.7
3.4
3.3
3.1
3.4
2.5
3.8
4.0
3.8
3.2
0.9
2.8
0.2
3.8
6.0
0.7
3.8
4.5
4.3
4.9
4.6
5.0
3.2
5.5
5.8
5.5
4.9
t/pixel
t/pixel
(ns)
(ns)
22
29
30
40
32
11
58
30
34
30
31
33
36
32
32
39
20
20
40
29
58
30
30
34
39
31
36
47
53
34
42
63
42
21
Table 14-10. Line start and pixel time for linear
model, SDRAM loaded 95%, priority delay = 16
14.6.6
The Priority Delay field in the Status register sets the time
the ICP will wait for SDRAM service before changing
from a low-priority bus request to a high-priority request.
The ICP normally requests SDRAM bus service at the
lowest-priority level, since it is a background processing
device. In some cases, service to the ICP could be con-
tinuously delayed by other background devices, such as
the VLD processor or by high-priority requests from the
DSPCPU.
The PD field sets a timer on the currently active bus re-
quest. The timer is loaded with the PD value and started
each time a bus request is submitted. The timer is incre-
mented once each block time, the time required to load
one block of 64 bytes. If the timer reaches 16 before the
request is serviced, the ICP changes its bus request pri-
ority from low to high.
The resulting time delay until the ICP changes to high pri-
ority is:
timer delay = (16 - PD)*(block time)
One block time is 16 clock cycles.
PRELIMINARY SPECIFICATION
horizontal filter, 1 component
horizontal filter, 3 components YUV422
vertical filter, 1 component
vertical filter, 3 components YUV 4:2:2
yuv to rgb8a, pci output
yuv to rgb15a, pci output
yuv to rgb24, pci output
yuv to rgb24a, pci output
yuv to rgb8a, sdram output
yuv to rgb15a, sdram output
yuv to rgb24, sdram output
yuv to rgb24a, sdram output
yuv to rgb8a, bitmask, pci output
yuv to rgb8a, rgbl15a overlay, pci output
yuv to rgb8a, rgbl24a overlay, pci output
yuv to rgb8a, yuv422a overlay, pci out-
put
yuv to rgb8a, 422sequencing, pci output
Priority Delay and ICP Minimum Bus
Bandwidth
function
Image Coprocessor
t/linestart
13.9
13.8
13.7
14.0
15.8
18.5
17.5
16.6
14.3
20.7
21.6
20.8
14.0
(µs)
2.9
8.7
0.4
1.2
t/pixel
14-21
(ns)
154
174
115
151
187
233
153
232
153
77
87
82
82
82
82
91
80