PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 169

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 11-2. Field values for Command Register
EM (Enable mastering). This bit controls the PNX1300
PCI interface’s ability to act as a PCI master. A value of
’0’ prevents the PCI interface from initiating PCI access-
es; a value of ’1’ allows the PCI interface to initiate PCI
accesses.
Note that the EM bit is automatically set to ’1’ whenever
the HE bit in the BIU_CTL register is set to ’1’ (see
tion 11.6.5, “BIU_CTL
abled for PNX1300 to serve as PCI host processor.
EM is set to ’0’ at power-up. Host system software can
set this bit to ’1’ with a configuration write.
SC (Special cycle). This bit controls PCI device recog-
nition of special-cycle operations. A value of ’0’ causes a
PCI device to ignore all special cycles; a value of ’1’ al-
lows a PCI device to monitor special cycle operations.
This bit is hardwired to ’0’ in PNX1300.
MWI (Memory write and invalidate). This bit deter-
mines a PCI device’s ability to generate memory-write-
and-invalidate commands. A value of ’1’ allows a PCI de-
vice to generate memory-write-and-invalidate com-
mands; a value of ’0’ forces the PCI device to use mem-
ory-write commands instead. PNX1300 implements this
bit. The conditions under which PNX1300 DMA transac-
tions generate memory-write-and-invalidate are de-
scribed in
tails of operation can be found in
Line Size Register.”
ways use regular memory-write transactions.
VGA (VGA palette snoop). This bit controls how VGA-
compatible PCI devices handle accesses to their palette
registers. This bit is hardwired to ’0’.
Figure 11-4. Status register format.
Reserved Write ignored; reads return 0
SERR#
Field
MWI
VGA
MA
EM
Par
I/O
SC
FB
Status Register
Section 11.6.16, “DMA_CTL Register.”
Hardwired to 0 (ignore I/O space accesses)
0 ⇒ no recognition of memory-space accesses
1 ⇒ recognizes memory-space accesses
0 ⇒ cannot act as PCI initiator
1 ⇒ can act as PCI initiator
Hardwired to 0 (ignore special cycle accesses)
0 ⇒ cannot generate memory write and invalidate
1 ⇒ can generate memory write and invalidate
Hardwired to 0
0 ⇒ ignore parity errors
1 ⇒ acknowledge parity errors
0 ⇒ disable driver for serr# pin
1 ⇒ enable driver for serr# pin
0 ⇒ fast back-to-back only to same agent
1 ⇒ fast back-to-back to different agents
Image Coprocessor DMA writes al-
Register”). Mastering must be en-
Value Explanation
DPE
15
SSE
14
Section 11.5.7, “Cache
RMA
13
RTA
12
STA
11
DEVSEL
10
Sec-
De-
9
DPD
8
PAR (Parity error response). This bit controls signaling
of parity errors (data or address). A value of ’0’ causes
the PCI interface to ignore parity errors; a value of ’1’
causes the PCI interface to report parity errors on the
perr# PCI signal. This bit is set to ’0’ at power-up; since
the PCI interface checks parity, software can set this bit
to ’1’ with a configuration write.
Wait (Wait-cycle control). This bit controls whether or
not a PCI device does address/data stepping. PCI devic-
es that never do stepping must hardwire this bit to 0.
Since PNX1300 does not implement stepping, this bit is
hardwired to ’0’.
SERR# (serr# enable). This bit enables the driver of the
serr# pin (system error): a value of ’0’ disables it, a value
of ’1’ enables it. All PCI devices that have an serr# pin
must implement this bit. This bit is set to ’0’ after reset; it
can be set to ’1’ with a configuration write. SERR# and
PAR must both be set to ’1’ to allow signaling of address
parity errors on the serr# signal.
FB (Fast back-to-back enable). This bit controls wheth-
er or not a PCI master can do fast back-to-back transac-
tions to different devices. A value of ’0’ means fast back-
to-back transactions are only allowed when the transac-
tions are to the same agent; a value of ’1’ means the
master is allowed to generate fast back-to-back transac-
tions to different agents. Initialization software will set
this bit if all targets are capable of fast back-to-back
transactions. In PNX1300, this bit is hardwired to ’0’.
Reserved. Reads from reserved bits returns ’0’; writes to
reserved bits cause no action.
11.5.4
The status register is used to record information about
PCI bus events. The status register format is shown in
Figure
Reserved. Reads from reserved bits return ’0’; writes to
reserved bits cause no action.
66M (66-MHz capable). This bit is hardwired to ’0’ for
PNX1300 (PCI runs at 33-MHz maximum).
UDF (user-definable features). Since the PNX1300
PCI interface does not implement PCI user-definable
features, this bit is hardwired to ’0’.
FBC (Fast back-to-backcapable). The PNX1300 PCI
interface does not support fast back-to-back capability,
so this bit is hardwired to ’0’.
DPD (Data parity detected). Since the PNX1300 PCI in-
terface can act as a PCI bus initiator, this bit is imple-
mented. DPD is set in the initiator’s status register when:
• The PAR (parity-error response) bit in the command
PRELIMINARY SPECIFICATION
FBC
register is set, and
7
UDF
11-4.
6
Status Register
66M
Table 11-3
5
4
Reserved
lists the Status register fields.
0
PCI Interface
11-5