PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 278

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Hierarchy also makes it easy and natural to allocate bus
bandwidth or latency to a group of units. Most bandwidth
or latency-demanding units are located at the top of the
hierarchy while the less demanding are at the bottom
and get a small amount of overall bandwidth.
Table 20-2. Minimum bandwidth allocation between
CPU caches and peripheral units.
20.4
In addition to the dual priority mechanism described in
Section
ture made of 6 fixed levels of hierarchy. This is combined
with a programmable weighted round robin algorithm per
level, as pictured in
Table 20-3. Arbitration weights at each level
The weights can be adjusted by software to allocate
bandwidth and latency depending on application require-
ments. Within a level of hierarchy the units can have
equal weights, giving them an equal share of bandwidth.
Alternatively, they can have different weights, giving
them an unequal share of the bandwidth for that level.
20-4
level 1: CPU MMIO, Dcache, Lcache are arbitrated with
level 2: VO unit has a programmable weight of 1, 3 or 5.
level 3: The ICP unit has a programmable weight of 1,3,5 or
level 5: The PCI unit has a programmable weight of 1,3 or 5.
level 6: Level 6 contains several lower bandwidth and/or
level 4 The VI unit has a programmable weight of 1 or 2.
Level
weight of
CPU and
caches
3
2
3
1
2
1
1
ARBITER ARCHITECTURE
20.2, PNX1300 supports an arbitration architec-
fixed priorities between each other and together
have a programmable weight of 1, 2 or 3.
Level 2 has a programmable weight of 1, 2 or 3.
Level 3 has a programmable weight of 1, 3, 5 or 7.
7. Level 4 has a programmable weight of 1,3 or 5.
Level 5 has a programmable weight of 1,3 or 5.
Level 6 has a programmable weight of 1 or 2.
latency-tolerant units. The VLD has a weight of 2. AI,
AO, DVDD and the boot block (only active during
booting) have a weight of 1.
weight of
level 2
Figure
1
1
2
1
3
2
3
PRELIMINARY SPECIFICATION
Arbitration Weights
20-5.
bandwidth
at level 1
75%
67%
60%
50%
40%
33%
25%
bandwidth
at level 2
25%
33%
40%
50%
60%
67%
75%
The arbitration weights at each level are described in
Table 20-3
Table 20-2
at Level 1 between the DSPCPU and the peripherals
(level 2) according to the different weight values that can
be programmed. Note that programming a weight of 3/3
or 2/2 instead of 1/1 is legal and results in the same allo-
cation.
Note: The different types of requests from the DSPCPU
caches are arbitrated locally before sending a single
CPU request to the arbiter. The PCI bus also performs lo-
cal arbitration before sending a system request to the ar-
biter.
The weight programming is done by setting the MMIO
register ARB_BW_CTL
description and coding is provided in
The hardware RESET value of ARB_BW_CTL is 0, re-
sulting in a weight of 1 for all requests.
Note that each media processor application needs to
carefully review its arbiter settings.
Table 20-4. ARB_BW_CTL MMIO register
0x100104
Offset
and illustrated in
arbitration
presents the minimum bandwidth allocation
level of
level 1
level 1
level 2
level 2
level 3
level 3
level 4
level 4
level 5
level 5
n/a
RESERVED 25:18
CPU weight 17:16
.
ICP weight
PCI weight
VO weight
L2 weight
L3 weight
L4 weight
L5 weight
L6 weight
VI weight
Register offset as well as field
field
Philips Semiconductors
Figure
20-5.
15:14
13:12
11:10
bits
9:8
7:6
4:3
2:1
Table
5
0
00 = weight 1
01 = weight 2
10 = weight 3
00 = weight 1
01 = weight 2
10 = weight 3
00 = weight 1
01 = weight 3
10 = weight 5
00 = weight 1
01 = weight 3
10 = weight 5
00 = weight 1
01 = weight 3
10 = weight 5
00 = weight 1
01 = weight 3
10 = weight 5
00 = weight 1
01 = weight 3
10 = weight 5
00 = weight 1
01 = weight 3
10 = weight 5
11 = weight 7
11 = weight 7
20-4.
0 = weight 1
1 = weight 2
0 = weight 1
1 = weight 2
allowed
values