PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 59

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

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Philips Semiconductors
Table 3-2. PCSW FP exception flag definitions
CS (Count Stalls). The CS flag determines the mode of
CCCOUNT, the 64-bit clock cycle counter. If CS = ‘1’, the
cycle counter increments on all clock cycles. If CS = ‘0’,
the clock cycle counter only increments on non-stall cy-
cles. See also
Counter.”
MSE and TRPMSE (Misaligned-Store Exception). The
MSE bit will be set when the processor detects a store
operation to an address that is not aligned. For example,
a 32-bit store executed with an address that is not a mul-
tiple of four will cause MSE to be set. The TRPMSE bit
enables the DSPCPU to raise misaligned address ex-
ceptions. An exception is requested if the intersection of
MSE and TRPMSE is non-zero. The acceptance and
handling of exceptions is described in
cial Event Handling.”
Unaligned load operations do not cause an exception,
because load operations can be speculative (i.e. their re-
sult is thrown away).
When the DSPCPU generates an unaligned address, the
low order address bit(s) (one bit in the case of a 16-bit
load, two bits for a 32-bit load) are forced to zero and the
load/store is executed from this aligned address.
WBE and TRPWBE (Write Back Error). The WBE flag
will be set whenever a program attempts to write back
more than 5 results simultaneously. This is indicative of
a programming error, likely caused by the scheduler or
assembler. The TRPWBE bit enables the corresponding
exception.
RSE, TRPRSE (Reserved Exception). RSE and TR-
PRSE are reserved for diagnostic purposes and not de-
scribed here.
TFE (Trap on First Exit). The TFE bit is a support bit for
the debugger. The TFE bit is set by the debugger prior to
taking a (non-interruptible) jump to the application pro-
gram. On the next interruptible jump (the first interrupt-
ible jump in the application being debugged), an excep-
tion is requested because the TFE bit is set. The
acceptance and handling of exception processing is de-
scribed in
responsibility of the exception handler software to clear
the TFE bit. The hardware does not clear or set TFE.
Corner-case note: Whenever a hardware update (e.g. an
exception being raised) and a software update (through
writepcsw) of the PCSW coincide, the new value of the
Flag
OVF Standard IEEE overflow flag
UNF Standard IEEE underflow flag
DBZ Standard IEEE divide-by-zero flag
OFZ ‘Output flushed to zero’ set if an operation caused a
INV
INX
IFZ
Standard IEEE invalid flag
Standard IEEE inexact flag
denormalized result
‘Input flushed to zero’ set if an operation was applied to
one or more denormalized operands
Section 3.5, “Special Event Handling.”
After RESET, CS is set to ‘1’.
Section 3.1.5, “CCCOUNT—Clock Cycle
Function
Section 3.5, “Spe-
It is the
PCSW will be the value that is written by the writepcsw
instruction, except for those bits that the hardware is cur-
rently updating (which will reflect the hardware value).
3.1.4
The SPC and DPC registers are support registers for ex-
ception processing. The DPC is updated during every in-
terruptible jump with the target address of that interrupt-
ible jump. If an exception is taken at an interruptible
jump, the value in the DPC register can be used by the
exception handling routine as the return address to re-
sume the program at the place of interruption.
The SPC register is updated during every interruptible
jump that is not interrupted by an exception. Thus on an
interrupted interruptible jump, the SPC register is not up-
dated. The SPC register allows the exception handling
routine to determine the start address of the decision tree
(a block of uninterruptible, scheduled PNX1300 code)
that was executing when the exception was taken (see
also
Corner-case note: Whenever a hardware update (during
an interruptible jump) and a software update (through
writedpc or writespc) coincide, the software update takes
precedence.
3.1.5
CCCOUNT is a 64-bit counter that counts clock cycles
since RESET. Cycle counting can occur in two modes,
depending on PCSW.CS. If PCSW.CS = ‘1’, the cycle
count increments on every CPU clock cycle. If PCSW.CS
= ‘0’, the clock cycle count only increments on non-stall
CPU cycles.
CCCOUNT is implemented as a master counter/slave
register pair. The master 64-bit counter gets updated
continuously. The value of the CCCOUNT slave register
is updated with the current master cycle count during
successful interruptible jumps only. The cycles and hicy-
cles DSPCPU operations return the content of the 32
LSBs and 32 MSBs, respectively, of the slave register.
This ensures that the value returned by hicycles and cy-
cles is coherent, as long as there is no intervening inter-
ruptible jump, which makes these operations suitable for
64-bit high resolution timing from C source code pro-
grams. The curcycles DSPCPU operation returns the 32
LSBs of the master counter. The latter operation can be
used for instruction cycle precise timing. When used, it
must be precisely placed, probably at the assembly code
level.
3.1.6
The bit pattern generated by boolean valued operations
(ileq, fleq etc.) is '00...00' (FALSE) or '00...01' (TRUE).
When interpreting a bit pattern as a boolean value, only
the LSB is taken into account, i.e. 'xx..x0' is interpreted
as FALSE and 'xx..x1' is interpreted as TRUE. In partic-
ular, wherever a general purpose register is used as a
‘guard’, the LSB determines whether execution of the
guarded operation takes place.
PRELIMINARY SPECIFICATION
Section 3.5, “Special Event
SPC and DPC—Source and
Destination Program Counter
CCCOUNT—Clock Cycle Counter
Boolean Representation
DSPCPU Architecture
Handling”).
3-3